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Topic: Vliw

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High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors
2011 / IEEE
By: Unekawa, Y.; Perre, L.; Fujisawa, T.; Vander Aa, T.; Suzuki, T.; Takeda, D.; Yamagishi, T.; Yamada, H.; Horisaki, K.;
BioThreads: A Novel VLIW-Based Chip Multiprocessor for Accelerating Biomedical Image Processing Applications
2012 / IEEE
By: Sijung Hu; Echiadis, A.; Jia Zheng; Azorin-Peris, V.; Chouliaras, V.; Stevens, D.;
Hybrid partitioned H.264 full high definition decoder on embedded quad-core
2012 / IEEE
By: Shihwa Lee; Do-Hyung Kim; Joon Ho Song; Minsoo Kim;
How to Square Floats Accurately and Efficiently on the ST231 Integer Processor
2011 / IEEE / 978-1-4244-9457-6
By: Jeannerod, C.-P.; Revy, G.; Monat, C.; Jourdan-Lu, J.;
LAPP: A Low Power Array Accelerator with Binary Compatibility
2011 / IEEE / 978-1-61284-425-1
By: Iwakami, T.; Devisetti, N.; Nakashima, Y.; Jun Yao; Nakada, T.; Yoshimura, K.;
Dynamic Reconfiguration for Irregular Code Using FNC-PAE Processor Cores
2011 / IEEE / 978-1-61284-425-1
By: Weinhardt, M.; May, F.; Vorbach, M.; Schuler, E.;
Performance and Power Analysis of ATI GPU: A Statistical Approach
2011 / IEEE / 978-0-7695-4509-7
By: Ying Zhang; Lu Peng; Bin Li; Yue Hu;
Techniques for improving coarse-grained reconfigurable architectures
2011 / IEEE / 978-1-61284-857-0
By: Jongeun Lee; Jong Kyung Paek; Kiyoung Choi; Seongsik Park; Kyuseung Han;
Address generation scheme for a coarse grain reconfigurable architecture
2011 / IEEE / 978-1-4577-1292-0
By: Hemani, A.; Shami, M.A.;
An efficient heuristic for instruction scheduling on clustered VLIW processors
2011 / IEEE / 978-1-4503-0713-0
By: Xuemeng Zhang; Jingling Xue; Hui Wu;
VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic
2011 / IEEE / 978-1-4577-1484-9
By: Jie Zhou; Yong Dou; Yuanwu Lei; Sufeng Wang;
An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating
2011 / IEEE / 978-1-4577-1048-3
By: Uchida, M.; Taniguchi, I.; Catthoor, F.; Raghavan, P.; Fukui, M.; Tomiyama, H.;
Semi-automation of Configuration Files Generation for Heterogeneous Multi-tile Systems
2011 / IEEE / 978-0-7695-4439-7
By: Rousseau, F.; Poste, N.; Chagoya-Garzon, A.;
A novel instruction scheduling scheme for clustered VLIW architecture
2011 / IEEE / 978-1-4244-9477-4
By: Ajayan, K.K.; Arafath, K.M.I.Y.;
Architecture design space exploration of run-time scalable issue-width processors
2011 / IEEE / 978-1-4577-0801-5
By: Koenig, R.; Becker, J.; Heisswolf, J.; Stripf, T.;
C++ Compiler Supports for Embedded Multicore DSP Systems
2011 / IEEE / 978-1-4577-1337-8
By: Chung-Kai Chen; Jia-Jhe Li; Chi-Bang Kuan; Jenq Kuen Lee;
An optimized TTA-like vertex shader datapath for embedded 3D graphics processing unit
2011 / IEEE / 978-1-4577-0170-2
By: Jizeng Wei; Jizhou Sun; Wei Guo; Yisong Chang;
Integration of code optimization and hardware exploration for a VLIW architecture by using fuzzy control system
2011 / IEEE / 978-1-4577-1617-1
By: Fettweis, G.; Xiaoyan Jia;
An approach to code compression for CGRA
2011 / IEEE / 978-1-4577-0144-3
By: Seongsik Park; Kiyoung Choi;
Design of configurable LFSR instructions targeted at stream cipher processing
2011 / IEEE / 978-1-4577-1997-4
By: Longmei Nan; Xuan Yang; Zibin Dai;
Architecture comparisons between Nvidia and ATI GPUs: Computation parallelism and data communications
2011 / IEEE / 978-1-4577-2064-2
By: Jianmin Chen; Jih-Kwon Peir; Bin Li; Lu Peng; Ying Zhang;
Research and implementation of micro-architecture for Elliptic Curve Cryptography processor
2011 / IEEE / 978-1-4577-1997-4
By: He Liangsheng; Chen Tao; Dai Zibin; Yang Xiaohui; Li Miao;
Flexible VLIW processor based on FPGA for real-time image processing
2011 / IEEE / 978-1-4577-0621-9
By: Fan Yang; Saptono, D.; Meunier, C.; Brost, V.;
Designing processors using MAsS, a modular and lightweight instruction-level exploration tool
2011 / IEEE / 978-1-4577-0621-9
By: David, R.; Thevenin, M.; Piriou, E.; Texier, M.;
Instruction Scheduling on Variable Latency Functional Units of VLIW Processors
2011 / IEEE / 978-1-4577-1880-9
By: Mujadiya, N.V.;
Scheduling for register file energy minimization in explicit datapath architectures
2012 / IEEE / 978-1-4577-2145-8
By: Mesman, B.; Yifan He; Dongrui She; Corporaal, H.;
A new SBST algorithm for testing the register file of VLIW processors
2012 / IEEE / 978-1-4577-2145-8
By: Reorda, M.S.; Sabena, D.; Sterpone, L.;
Low-power video decoding system using a reconfigurable processor
2012 / IEEE / 978-1-4577-0231-0
By: Won Chang Lee; Joon Ho Song; Shihwa Lee; Do-Hyung Kim; Doo Hyun Kim;
Design smart antenna for GPS/GLONASS using adaptive beamforming
2012 / IEEE / 978-617-607-138-9
By: Herasymenko, K.V.; Laush, A.G.; Dubrovka, F.F.;
A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture
2012 / IEEE / 978-1-4577-2145-8
By: Stripf, T.; Becker, J.; Koenig, R.;
A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS
2012 / IEEE / 978-1-4673-0438-2
By: Damodaran, R.; Anderson, T.; Sussman, R.; Peavy, K.; Hales, A.; Wu, D.; Narnur, S.; Rajagopal, A.; Flores, J.; Mahmood, N.; Olorode, O.; Gurram, K.; Thompson, D.; Ong, H.; Mullinnix, S.; Pierson, M.; Moharil, S.; Rahman, M.; Bui, D.; Tran, J.; Bhoria, N.; Balasubramanian, D.; Chachad, A.; Hill, A.; Gopalakrishnan, D.; Gill, M.; Venkatasubramanian, R.; Agarwala, S.;
An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC cores
2012 / IEEE / 978-1-4673-1188-5
By: Koal, T.; Scholzel, M.; Vierhaus, H.T.;
Effective programming of very long instruction word digital signal processors
2012 / IEEE / 978-80-214-4470-6
By: Marsalek, R.; Fryza, T.; Adamec, F.;
Trimmed VLIW: Moving application specific processors towards high level synthesis
2012 / IEEE / 978-2-9539987-1-9
By: Taemin Kim; Irturk, A.; Oberg, J.; Matai, J.; Kastner, R.;
Architecture Design Trade-offs among VLIW SIMD and Multi-core Schemes
2012 / IEEE / 978-1-4673-0974-5
By: Chen, Xiaowen; Chen, Hu; Zhang, Kai; Chen, Shuming; Wang, Yaohua;
VLIW - SIMD processor based scalable architecure for parallel classifier node computing
2013 / IEEE
By: Ganapathi Puppala, Venkata;
BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture
2013 / IEEE
By: Atak, O.; Atalar, A.;
Aging-aware compiler-directed VLIW assignment for GPGPU architectures
2013 / IEEE
By: Gupta, Rajesh K.; Benini, Luca; Rahimi, Abbas;
Accelerating gesture recognition algorithm using coarse grained reconfigurable architectures
2014 / IEEE
By: Sung, Minyong; Kim, Deokho; Kim, Minsik; Ro, Won Woo; Kim, Jaehyun; Lee, Wonjae;
RTL implementation for a specific ALU of the 32-bit VLIW DSP processor core
2014 / IEEE
By: Dinh-Duc, Anh-Vu; Le-Huu, Khoi-Nguyen; Bui, Trong-Tu; Dang-Do, Quoc-Minh;
Efficient implementation of the row-column 8×8 IDCT on VLIW architectures
1998 / IEEE
By: Eisenbeis, Christine; Sakellariou, Rizos; Knijnenburg, Peter;
A micro-architecture design for the 32-bit VLIW DSP processor core
2014 / IEEE
By: Le-Huu, Khoi-Nguyen; Nguyen, Tin T.; Dinh-Duc, Anh-Vu;
Comparison of the software defined radio implementations of the K-best list sphere detection
2009 / IEEE
By: Silven, Olli; Janhunen, Janne; Juntti, Markku;
Fast enumeration-based modulo scheduling heuristic for VLIW architectures
2014 / IEEE
By: Elleaume, P.; Belkouch, S.; Bahtat, M.; Gall, P.L.;
Modulo scheduler implementation for VLIW processor
2014 / IEEE
By: Ingoo Heo; Hyungyun Jung; Sangjun Han; Jangseop Shin; Yunheung Paek;
Always-on Vision Processing Unit for Mobile Applications
2015 / IEEE
By: Connor, Fergal; Brick, Cormac; Barry, Brendan; Toma, Vasile; O'Riordan, Martin; Richmond, Richard; Moloney, David; Donohoe, David;
20-Bit RISC and DSP System Design in an FPGA
2014 / IEEE
By: Jain, Rita; Tomar, Amit Kumar Singh;
Reconfigurable high performance architectures: How much are they ready for safety-critical applications?
2014 / IEEE
By: Sabena, D.; Sterpone, L.; Hagemeyer, J.; Porrmann, M.; Stender, C.; Rittner, F.; Glein, R.; Wong, S.; Vierhaus, H. T.; Koal, Tobias; Scholzel, Mario;
Special session speaker's biography
2014 / IEEE
Compiler-Assisted Leakage- and Temperature- Aware Instruction-Level VLIW Scheduling
2014 / IEEE
By: Cao, S.; Wei, S.; Wang, F.; Li, Z.;
Automatic complex instruction identification for efficient application mapping onto ASIPs
2014 / IEEE
By: Nery, Alexandre S.; Corporaal, Henk; Jozwiak, Lech; Franca, Felipe M. G.; Nedjah, Nadia;
A VLIW-Vector co-processor design for accelerating Basic Linear Algebraic Operations in OpenCV
2014 / IEEE
By: Puppala, Venkata Ganapathi;
A High-Utilization Scheduling Schemeof Stream Programs on ClusteredVLIW Stream Architectures
2014 / IEEE
By: Li, Z.; Jiang, G.; Wei, S.; Wang, F.;
Processor Design with Asymmetric Reliability
2014 / IEEE
By: Chattopadhyay, Anupam; Paul, Goutam; Wang, Zheng;
Low-power vectorial VLIW architecture for maximum parallelism exploitation of dynamic programming algorithms
2014 / IEEE
By: Cruz, Miguel; Roma, Nuno; Tomas, Pedro;
A Tiny Scale VLIW Processor for Real-Time Constrained Embedded Control Tasks
2014 / IEEE
By: Stecklina, Oliver; Methfessel, Michael;
ePUMA: A unique memory access based parallel DSP processor for SDR and CR
2013 / IEEE
By: Liu, Dake; Wang, Jian; Sohl, Joar; Karlsson, Andreas;
Embedded reconfigurable computing: the ERA approach
2013 / IEEE
By: Keramidas, G.; Spiliopoulos, V.; Goel, B.; Mckee, S.A.; Kavvadias, S.; Giorgi, R.; Wong, S.; Carro, L.; Scordino, C.; Seedorf, R.; Brandon, A.; Anjam, F.; Matos, D.;
A proposed RISC instruction set architecture for the MAC unit of 32-bit VLIW DSP processor core
2014 / IEEE
By: Vu, Thanh; Dinh-Duc, Anh-Vu; Le-Huu, Khoi-Nguyen; Bui, Trong-Tu; Luu, Vy; Dang-Do, Quoc-Minh;
A failure to communicate: Security vulnerabilities in the GridStreamX Edgeware application
2013 / IEEE
By: Kaarst-Brown, Michelle; Brooks, Tyson; McKnight, Lee; Joon Park; Caicedo, Carlos;
Session 18: Ubi/cloud computing
2013 / IEEE
By: Zhang, Tiejun; Xu, Si; Bao, Lidan; Hou, Chaohuan; Wang, Donghui;
Adaptive real-time DSP acceleration for SoC applications
2014 / IEEE
By: Savaria, Yvon; Bois, Guy; Nsame, Pascal;
Tool for algorithms mapping with help of signal-flow graph approach
2014 / IEEE
By: Mego, Roman; Fryza, Tomas;
Opportunistic redundancy for improving reliability of embedded processors
2013 / IEEE
By: Wang, Zheng; Chattopadhyay, Anupam; Li, Renlin;
Time-critical computing on a single-chip massively parallel processor
2014 / IEEE
By: van Amstel, Duco; de Dinechin, Benoit Dupont; Lager, Guillaume; Poulhies, Marc;
Lifetime holes aware register allocation for clustered VLIW processors
2014 / IEEE
By: Sun, Haiyan; Wu, Hui; Zhang, Xuemeng; Xue, Jingling;
A VLIW architecture for a trace scheduling compiler
1988 / IEEE
By: O'Donnell, J.J.; Nix, R.P.; Colwell, R.P.; Rodman, P.K.; Papworth, D.B.;
HPSm2: A refined single-chip microengine
1988 / IEEE / 0-8186-0841-2
By: Hwu, W.W.; Patt, Y.N.;
A programmable hardware accelerator for compiled electrical simulation
1988 / IEEE / 0-8186-0864-1
By: Lewis, D.M.;
CREATE-LIFE: a design system for high performances VLSI circuits
1988 / IEEE / 0-8186-0872-2
By: Slavenburg, G.A.; Labrousse, J.;
Compiling on Horizon
1988 / IEEE / 0-8186-0882-X
By: Draper, J.M.;
Squeezing more CPU performance out of a Cray-2 by vector block scheduling
1988 / IEEE / 0-8186-0882-X
By: Lichnewsky, A.; Jalby, W.; Eisenbeis, C.;
Scalar supercomputer architecture
1989 / IEEE
By: Weiss, S.;
The potential for parallel processing and neural computing in management decision support
1989 / IEEE / 0-8186-1913-9
By: Turban, E.; Trippi, R.;
The i960CA SuperScalar implementation of the 80960 architecture
1990 / IEEE / 0-8186-2028-5
By: McGeady, S.;
CREATE-LIFE: a modular design approach for high performance ASICs
1990 / IEEE / 0-8186-2028-5
By: Labrousse, J.; Slavenburg, G.A.;
A performance comparison of the IBM RS/6000 and the Astronautics ZS-1
1991 / IEEE
By: Davidson, E.S.; Abraham, S.G.; Mangione-Smith, W.;
Toward advanced parallel processing: exploiting parallelism at task and instruction levels
1991 / IEEE
By: Fukuda, A.; Tomita, S.; Murakami, K.;
A restructurable VLSI robotics vector processor architecture for real-time control
1989 / IEEE
By: Orin, D.E.; Olson, K.W.; Ling, Y.-L.C.; Sadayappan, P.;
Computer architectures for robot control: a comparison and a new processor delivering 20 real MFLOPS
1989 / IEEE / 0-8186-1938-4
By: Andersson, R.L.;
A flexible high performance 2-D discrete cosine transform IC
1989 / IEEE
By: McSweeney, B.; Chong, D.; Matterne, L.; Woudsma, R.;
A study of time-redundant fault tolerance techniques for high-performance pipelined computers
1989 / IEEE / 0-8186-1959-7
By: Franklin, M.; Sohi, G.S.; Saluja, K.K.;
A 500 MHz microprocessor with a very long instruction word architecture
1990 / IEEE
By: Labrousse, J.; Slavenburg, G.A.;
Synthesis using path-based scheduling: algorithms and exercises
1990 / IEEE / 0-89791-363-9
By: Bergamaschi, R.A.; Camposano, R.;
An 80-MFLOPS (peak) 64-b microprocessor for parallel computer
1992 / IEEE
By: Nakano, H.; Nakajima, M.; Nakakura, Y.; Yoshida, T.; Kadota, H.; Nakai, Y.; Segawa, R.; Kishida, T.; Goi, Y.;
Xputers: very high throughput by innovative computing principles
1990 / IEEE / 0-8186-2078-1
By: Hirschbiel, A.G.; Hartenstein, R.W.; Weber, M.;
A superpipeline approach to the MIPS architecture
1991 / IEEE / 0-8186-2134-6
By: Lui, I.; Bashteen, A.; Mullan, J.;
Parallelization of loops with exits on pipelined architectures
1990 / IEEE / 0-8186-2056-0
By: Lee, M.; Tirumalai, P.; Schlansker, M.;
Architecture and implementation of a VLIW supercomputer
1990 / IEEE / 0-8186-2056-0
By: Joshi, C.S.; Hall, W.E.; Colwell, R.P.; Tornes, J.E.; Rodman, P.K.; Papworth, D.B.;
The design of a RISC based multiprocessor chip
1990 / IEEE / 0-8186-2056-0
By: Epstein, M.; Gupta, R.; Whelan, M.;
An investigation of static versus dynamic scheduling
1990 / IEEE / 0-8186-2047-1
By: Love, C.E.; Jordan, H.F.;
Multiple instruction issue in the NonStop Cyclone processor
1990 / IEEE / 0-8186-2047-1
By: Jardine, R.L.; Harris, R.L.; Horst, R.W.;
The impact of synchronization and granularity on parallel systems
1990 / IEEE / 0-8186-2047-1
By: Su, H.-M.; Chen, D.-K.; Yew, P.-C.;
Balance in architectural design
1990 / IEEE / 0-8186-2047-1
By: Snyder, L.; Ho, S.;
Boosting beyond static scheduling in a superscalar processor
1990 / IEEE / 0-8186-2047-1
By: Smith, M.D.; Horowitz, M.A.; Lam, M.S.;
Exploiting instruction-level resource parallelism for transparent, integrated control-flow monitoring
1991 / IEEE / 0-8186-2150-8
By: Shen, J.P.; Schuette, M.A.;
A 54*54-b regularly structured tree multiplier
1992 / IEEE
By: Nakajima, M.; Sato, T.; Goto, G.; Sukemura, T.;
VLIW-in-the-large: a model for fine grain parallelism exploitation on distributed memory multiprocessors
1990 / IEEE / 0-8186-2124-9
By: Vanneschi, M.; Danelutto, M.;
A software pipelining based VLIW architecture and optimizing compiler
1990 / IEEE / 0-8186-2124-9
By: Yimin Wu; Wei Zhao; Zhizhong Tang; Jian Wang; Bogong Su;
A fine-grained MIMD architecture based upon register channels
1990 / IEEE / 0-8186-2124-9
By: Gupta, R.;

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