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Topic: Vhdl Language

Results

VHDL Implementation of a Flexible and Synthesizable FFT Processor

2012 / IEEE
By: Correa, I.S.; Costa, J.C.W.A.; Klautau, A.; Freitas, L.C.;

An FPGA implementation and performance evaluation of the seed block cipher

2011 / IEEE / 978-1-4577-0274-7
By: Kitsos, P.; Skodras, A.N.;

Fault-tolerance assessment and enhancement in SoCWire interface: A system-on-chip wire

2011 / IEEE / 978-1-4577-1056-8
By: Salamat, R.; Zarandi, H.R.;

Hardware implementation of FIR filter

2011 / IEEE / 978-1-61284-774-0
By: Xiao-li Hu; Min Zhang; Feng-ying Wang;

The study of the measured frequency in EPM3128 based on the VHDL language

2011 / IEEE / 978-1-4244-9600-6
By: Ding Qian; Lian Ya-fei; Zhang Zi-sheng; Li Guan; Ji Ying-chao;

The design of five-stage pipeline CPU based on MIPS

2011 / IEEE / 978-1-4244-8165-1
By: Hui Ma; Dinglei Wang;

Design QC-LDPC coder based on FPGA

2011 / IEEE / 978-1-4244-8165-1
By: Jing Li; He Guan; Mingchuan Meng;

Novel on-chip sine wave generator

2011 / IEEE / 978-1-4577-1411-5
By: Bohrn, M.; Vrba, R.; Fujcik, L.;

An FPGA Implementation of the ZUC Stream Cipher

2011 / IEEE / 978-1-4577-1048-3
By: Skodras, A.N.; Sklavos, N.; Kitsos, P.;

QPSK Modulator on FPGA

2011 / IEEE / 978-1-4577-1974-5
By: Ianchis, D.; Gontean, A.S.; Popescu, S.O.;

Design of radar co-controller based on FPGA

2011 / IEEE / 978-1-4244-8165-1
By: Minggang Chai; Aiyu Lu; Zhidong Shao;

Assertion support in high-level synthesis design flow

2011 / IEEE / 978-2-9530504-4-8
By: Ribon, A.; Dallet, D.; Jego, C.; Le Gal, B.;

Design, simulation and synthesis of wheelchair controller using Fuzzy logic

2011 / IEEE / 978-1-61284-846-4
By: Othman, M.; Ali, S.H.M.; Sarker, M.R.; Islam, S.; Majlis, B.Y.;

A novel practical approach for establishing security in the communication satellites

2011 / IEEE / 978-1-4577-2019-2
By: Keyghobad, K.; Chegini, A.;

Design of (15, 11) Hamming Code Encoding and Decoding System Based on FPGA

2011 / IEEE / 978-0-7695-4519-6
By: Tongsheng Zhang; Qun Ding;

Design and Implementation of CRC Based on FPGA

2011 / IEEE / 978-1-4577-1219-7
By: Tongsheng Zhang; Qun Ding;

Design of the Multi-encrypted Circuit Based on FPGA

2011 / IEEE / 978-1-4577-1419-1
By: Minggang Chai; Xia Hai; Min Chen;

HW/SW TQ/IQT design for H.264/AVC

2011 / IEEE / 978-1-4577-1846-5
By: Masmoudi, N.; Loukil, H.; Ben Atitallah, A.;

The design of cyclic redundancy check module based on FPGA

2011 / IEEE / 978-1-4673-1690-3
By: Guo Ying; Yu Zong-zuo;

Automatic FFT code generation for FPGAs with high flexibility and human readability

2011 / IEEE / 978-1-4673-0323-1
By: O'Sullivan, J.; Rice, G.; Weiss, S.;

BPSK system on Spartan 3E FPGA

2012 / IEEE / 978-1-4577-0197-9
By: Budura, G.; Gontean, A.S.; Popescu, S.O.;

A generalized waveform identifier technique for Software Radio

2012 / IEEE / 978-1-4673-0276-0
By: Rinaldi, C.; Colizza, M.; Senese, I.J.;

FPGA implementation of predictive control

2012 / IEEE / 978-1-4673-0784-0
By: Aridhi, E.; Mami, A.; Abbes, M.;

An MPEG-4 AAC decoder FPGA implementation for the Brazilian digital television

2012 / IEEE / 978-1-4673-0186-2
By: Susin, A.A.; Renner, A.;

How the CRC algorithm in Xmodem protocol implementation in FPGA

2012 / IEEE / 978-1-4577-1415-3
By: Yuan Wang; Ming Cheng;

Application of the DLFSR generators in spread spectrum communication

2012 / IEEE / 978-83-932075-8-9
By: Stepien, R.; Walczak, J.;

A state-of-the-art VHDL simulator

1988 / IEEE / 0-8186-0828-5
By: Stanculescu, A.G.; Coelho, D.R.;

An electro-optical standard-cell for ASIC design

1994 / IEEE / 0-7803-2020-4
By: Seyfou, S.; Auletta, R.;

VHDL for FPGA design

1993 / IEEE / 0-7803-9970-6
By: Olsen, G.; McDermith, W.;

1995 high level synthesis design repository

1995 / IEEE / 0-8186-7076-2
By: Dutt, N.D.; Panda, P.R.;

ASIC BIST synthesis: a VHDL approach

1996 / IEEE / 0-7803-3541-4
By: Meyers, C.; McVay, B.; Eberle, T.; Moore, J.;

Synthesis of multi-dimensional applications in VHDL

1996 / IEEE / 0-8186-7554-3
By: Passos, N.L.; Sha, E.H.-M.;

Stimuli generator dedicated for an implantable visual miniaturized stimulator

1995 / IEEE / 0-7803-2475-7
By: Boyer, A.; Sawan, M.;

Comparative design methodologies for FPGA based computer arithmetic

1997 / IEEE / 0-8186-7873-9
By: Hix, R.W., Jr.; Haggard, R.L.;

Evolving standards and methodologies for electronic systems design

1997 / IEEE / 0-7803-3725-5
By: Peterson, G.D.;

A reconfigurable and flexible parallel 3D vision system for a mobile robot

1993 / IEEE / 0-8186-5420-1
By: Trihandoyo, A.; Mayorquim, J.L.; Meribout, M.; Shawky, M.; Jardin, B.; Tu, X.W.; Yao, E.; Belloum, A.; Hou, K.M.;

VLSI design and realisation of a 4 input high speed fuzzy processor

1997 / IEEE / 0-7803-3796-4
By: Gandolfi, E.; Gabrielli, A.; Roch, M.R.; Masetti, M.;

A CMOS implementation of a Connex memory

1997 / IEEE / 0-7803-3804-9
By: Mitu, B.; Ilas, M.;

A case study in the development of multi-media educational material: the VHDL interactive tutorial

1997 / IEEE
By: Famorzadeh, S.; Egolf, T.; Madisetti, V.K.; Klenke, R.H.; Salinas, M.H.; Karns, L.N.; Aylor, J.H.; Taylor, T.C.; Stinson, J.A., Jr.; Gadient, A.J.; Carter, H.W.;

Design of a classification system for rectangular shapes using a co-design environment

2000 / IEEE / 0-7695-0843-X
By: Engel, P.M.; Molz, R.F.; Robert, M.; Torres, L.; Moraes, F.G.;

PLD implementation of neural network for industrial gas discrimination system

2001 / IEEE / 0-7803-7090-2
By: Wan-Young Chung; U-Trum Jang;

A reconfigurable linear feedback shift register (LFSR) for the Bluetooth system

2001 / IEEE / 0-7803-7057-0
By: Koufopavlou, O.; Zervas, N.; Sklavos, N.; Kitsos, P.;

Designing of LAN models for diagnosis problem solving

2001 / IEEE / 966-553-079-8
By: Hafil, I.M.; Zanuneh, A.; Babich, A.V.; Hahanov, V.I.;

Implementation of a fast algorithm to find data clusters

2001 / IEEE / 0-7803-7324-3
By: Qichun Xu; Martin, M.I.;

Algorithm of cubic coverage building for circuits with flip-flop structures (modified /spl pi/-algorithm)

2002 / IEEE / 966-553-234-0
By: Skvortsova, O.; Yegorov, O.; Chamyan, H.;

The fuzzy controller by programmable logic circuit

2002 / IEEE / 0-7803-7268-9
By: Yuntian Qu; Luyi Xia;

An efficient implementation of the digital signature algorithm

2002 / IEEE / 0-7803-7596-3
By: Kitsos, P.; Koufopavlou, O.; Sklavos, N.;

Simulation environment to verify industrial communication circuits

2002 / IEEE / 0-7803-7474-6
By: Fernandez, E.; Jimenez, J.; Zuloaga, A.; Bidarte, U.; Martin, J.L.;

Different proposals to the multiplication of 3/spl times/3 vision mask in VHDL for FPGA's

2003 / IEEE / 0-7803-7937-3
By: Hernandez, A.; Bravo, I.; Diaz, V.; Lazaro, J.L.; Mateos, R.; Gardel, A.;

A system level IP integration methodology for fast SOC design

2003 / IEEE / 0-7803-8160-2
By: De Bartolomeis, C.; Brunelli, C.; Bocchi, M.; Campi, F.; Magagni, L.;

An end-to-end hardware approach security for the GPRS

2004 / IEEE / 0-7803-8271-4
By: Koufopavlou, O.; Sklavos, N.; Kitsos, P.;

A remote laboratory for debugging FPGA-based microprocessor prototypes

2004 / IEEE / 0-7695-2181-9
By: Gomez-Arribas, F.; Lopez, J.; Gonzalez, I.; Pastor, J.S.; Martinez, J.;

Towards MPEG-4 part 10 system on chip: a VLSI prototype for context-based adaptive variable length coding (CAVLC)

2004 / IEEE / 0-7803-8504-7
By: Jullien, G.; Badawy, W.; Amer, I.;

Hardware implementation of a fault recovery protocol compliant with interbus-S standard

2004 / IEEE / 0-7803-8730-9
By: Mita, R.; Palumbo, A.; Cavalieri, S.; Palumbo, G.;

Fully parametrable downsampler generator

2004 / IEEE / 0-7803-8689-2
By: Naviner, J.-F.; Naviner, L.A.B.; de Barros, M.A.;

Research on quadrature transformation structures for SDR receiver

2005 / IEEE / 0-7803-9015-6
By: Canyan Zhu;

Hardware implementation of the RC4 stream cipher

2003 / IEEE / 0-7803-8294-3
By: Kostopoulos, G.; Kitsos, P.; Koufopavlou, O.; Sklavos, N.;

VHDL implementation of a neural diagnosis system: application to induction machine fault detection

2004 / IEEE / 0-7803-8304-4
By: Dumartin, T.; Grisel, R.; Cirrincione, G.;

An active methodology for teaching electronic systems design

2006 / IEEE
By: Peiro, M.A.; Boluda, J.C.; Palero, R.J.C.; Girones, R.; Torres, M.A.L.;

Novel Architecture for IEEE-754 Standard

2006 / IEEE / 0-7803-9521-2
By: Dadkhahi, N.; Mirbaha, A.; Kavehie, O.; Navi, K.;

Hardware Realization Of The MPEG-7 Edge Histogram Descriptor

2006 / IEEE / 83-922632-2-7
By: Rudnicki, R.; Sniatala, P.; Rybarczyk, A.; Kapela, R.;

An FPGA hardware implementation of the Rijndael block cipher

2006 / IEEE / 0-7803-9726-6
By: Dhoha, C.; Ben Saoud, S.; Ben Othman, S.;

HW/SW Codesign of the H. 263 Video Coder

2006 / IEEE / 1-4244-0038-4
By: Ghozzi, P.; Kadionik, P.; Atitallah, A.B.; Levi, H.; Masmoudi, N.; Nouel, P.;

Implementation in Fpgas of Jacobi Method to Solve the Eigenvalue and Eigenvector Problem

2006 / IEEE / 1-4244-0312-X
By: Gardel, A.; Lazaro, J.L.; Mazo, M.; Jimenez, P.; Bravo, I.;

Architecture of an HDTV Intraframe Predictor for a H.264 Decoder

2006 / IEEE / 3-901882-19-7
By: Susin, A.A.; Berriel, E.A.; Staehler, W.T.; Bampi, S.;

Optimization of Behavioral Modeling for Codesign of Embedded System

2007 / IEEE / 1-4244-0996-9
By: RajaPaul Perinbam, J.; Sangeetha, M.;

FPGA as a Tool for Implementing Non-fixed Structure Fuzzy Logic Controllers

2007 / IEEE / 1-4244-0703-6
By: Castillo, O.; Gonzalez, J.L.; Aguilar, L.T.;

A modular VLIW Processor

2007 / IEEE / 1-4244-0920-9
By: Brost, V.; Paindavoine, M.; Fan Yang;

An Efficient HW/SW Implementation of the H.263 Video Coder in FPGA

2006 / IEEE / 1-4244-0394-4
By: Kadionik, P.; Ben Atitallah, A.; Levi, H.; Masmoudi, N.; Nouel, P.; Ghozzi, F.;

Development of a Fuzzy Logic Controller Algorithm for Air-conditioning System

2006 / IEEE / 0-7803-9730-4
By: Ahmed Rafi, K.A.; Zaman Sarker, M.S.; Islam, M.S.; Othman, M.;

Obfuscation as Intellectual Rights Protection in VHDL Language

2007 / IEEE / 0-7695-2894-5
By: Yarmolik, V.N.; Brzozowski, M.;

High-Speed Method of Hardware Simulation

2007 / IEEE / 966-533-587-0
By: Hahanov, V.; Radivilova, T.; Ghribi, W.; Kteiman, H.; Kamenuka, E.;

Real-Time Signal Processing of Infrasound Data Using 1D Wavelet Transform on FPGA Device

2007 / IEEE / 978-1-4244-0866-5
By: Chilo, J.; Lindblad, T.;

Tool for Simulation and Optimization BIST Structures

2007 / IEEE / 978-1-4244-0812-2
By: Gosciniak, I.;

HW/SW FPGA implementation of Vector Median Filter

2007 / IEEE / 978-1-4244-1000-2
By: Masmoudi, N.; khriji, L.; Kadionik, P.; Ben Atitallah, A.; Boudabous, A.;

HW/SW FPGA Architecture for a Flexible Motion Estimation

2007 / IEEE / 978-1-4244-1377-5
By: Ben AtItallah, A.; Levi, H.; Masmoudi, N.; KadIonik, P.;

Modeling and simulation of photovoltaic panel based on artificial neural networks and VHDL-language

2007 / IEEE / 978-1-4244-1377-5
By: Salhi, H.; Mellit, A.; Mekki, H.; Khaled, B.;

An efficient VLSI architecture for rate disdortion optimization in AVS video encoder

2008 / IEEE / 978-1-4244-1683-7
By: Hai bing Yin; Wen Gao; Zhe Lei Xia; Xi Zhong Lou;

Petri Net Based Rapid Prototyping of Digital Complex System

2008 / IEEE / 978-0-7695-3170-0
By: Andreu, D.; Gil, T.; Souquet, G.;

FPGA based control IC for multilevel inverter

2008 / IEEE / 978-1-4244-1691-2
By: Rahim, H.A.; Ahmad, R.B.; Husin, Z.; Ahmad, M.I.; Md Isa, M.N.; Abu Hassan, M.S.;

FPGA-based implementation of hardware technology on Generic Algorithms

2008 / IEEE / 978-1-4244-1733-9
By: Wang Yu-Ti; Zhong Wei-Sheng; Zeng Xiao-Shu;

FPGA-based controllers for switching converters

2008 / IEEE / 978-1-4244-1741-4
By: Jezernik, K.;

The Design and Implementation of Zero-Copy for Linux

2008 / IEEE / 978-0-7695-3382-7
By: Zhou Chuansheng; Chang Guiran; Zhu Hongfeng; Liu Tianhua;

Remodeling of fuzzy PID controller based on dynamic NN

2008 / IEEE / 978-1-889335-38-4
By: Yingying Su; Taifu Li; Bingxiang Zhong; Yonggang Liu;

FPGA Codesign Implementation of Vector Directional Filter

2008 / IEEE / 978-1-4244-3321-6
By: Kadionik, P.; Ben Atitallah, A.; Boudabous, A.; Masmoudi, N.; Khriji, L.;

A secure Elliptic Curve Digital Signature scheme for embedded devices

2008 / IEEE / 978-1-4244-2627-0
By: Mohsen, M.; Wajih, E.H.Y.; Rached, T.;

Hardware acceleration of approximate palindromes searching

2008 / IEEE / 978-1-4244-2795-6
By: Lexa, M.; Martinek, T.;

Three-dimensional motion control using embedded controller and FPGA technology

2008 / IEEE / 978-1-4244-2014-8
By: Dhanashri; Kamble, R.D.; Satyam; Sharma, V.K.;

Design of a Digital Programmable Control IC for Single-Phase Controlled Rectifiers

2006 / IEEE / 1-4244-0448-7
By: Ming-Fa Tsai; Jui-Kum Wang; Ying-De Lin; Fu-Jing Ke;

A multi-threaded DNA tag/anti-tag library generator for multi-core platforms

2009 / IEEE / 978-1-4244-2756-7
By: Burns, D.J.; Ravindran, A.;

An Analysis of Fault Effects and Propagations in AVR Microcontroller ATmega103(L)

2009 / IEEE / 978-1-4244-3572-2
By: Zarandi, H.R.; Rohani, A.;

A 65 nm CMOS digital processor for multi-mode time interleaved high-pass �� A/D converters

2009 / IEEE / 978-1-4244-3827-3
By: Naviner, L.; Nguyen, V.-T.; Beydoun, A.; Loumeau, P.;

Design of a digital control IC of a current source based on a three-phase controlled rectifier

2009 / IEEE / 978-1-4244-3556-2
By: Li-Ching Hsiao; Fu-Jing Ke; Ming-Fa Tsai; Jui-Kum Wang;

Research and implementation of a novel single phase AC/AC variable frequency technology

2009 / IEEE / 978-1-4244-3556-2
By: Weihua Wu; Xiaohu Cao; Hong Zhu; Shicheng Zheng; Qianzhi Zhou;

FPGA-based controllers for switching converters

2009 / IEEE / 978-1-4244-3860-0
By: Jezernik, K.;

FPGA-based MSK DS-SS modulator for digital satellite communications

2009 / IEEE / 978-1-4244-4214-0
By: Maghawry, A.; Eldiwany, E.;

Design and implementation of an android

2009 / IEEE / 978-1-4244-4479-3
By: Juarez, J.I.G.; Rodriguez, N.E.C.; Fernandez, M.R.L.; Savage, R.;

Design and optimization of ColdFire CPU Arithmetic Logical Unit

2009 / IEEE / 978-1-4244-4798-5
By: Fryza, T.; Adamec, F.;

A 65 nm CMOS versatile ADC using time interleaving and �� modulation for multi-mode receiver

2009 / IEEE / 978-1-4244-4573-8
By: Jabbour, C.; Beydoun, A.; Loumeau, P.; Naviner, L.; Nguyen, V.-T.; Fakhoury, H.;

Design and Implement of Digital Modulator Based on Improved DDS Technology and DSP Builder

2009 / IEEE / 978-1-4244-3691-0
By: Xiaoqiao Lu; Kangshun Li; Feng Wang; Wensheng Zhang;

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