Your Search Results

Use materials about this topic in your textbook!

AcademicPub holds over eight million pieces of educational content - such as case studies and journal articles - for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!

Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

Topic: Retiming

Results

Efficient Retiming of Multirate DSP Algorithms

2012 / IEEE
By: Geilen, M.; Basten, T.; Xue-Yang Zhu; Stuijk, S.;

Compilation of stream programs onto scratchpad memory based embedded multicore processors through retiming

2011 / IEEE / 978-1-4503-0636-2
By: Chatha, K.; Weijia Che;

Implementation of the echo cancellation for DTMB repeater

2011 / IEEE / 978-1-61284-722-1
By: Jianghong Shi; Jiangnan Yuan; Renjie Su;

An algorithmic transformation for FPGA implementation of high throughput filters

2011 / IEEE / 978-1-4577-0768-1
By: Kamboh, H.M.; Khan, S.A.;

Latch-Based Performance Optimization for FPGAs

2011 / IEEE / 978-1-4577-1484-9
By: Anderson, J.H.; Bill Teng;

A Fast Retiming Algorithm Integrated with Rewiring for Flip-Flop Reductions

2011 / IEEE / 978-1-4577-1079-7
By: Yi Diao; Yuliang Wu;

High-speed and low-power ASIC implementation of OFDM transceiver based on WLAN (IEEE 802.11a)

2012 / IEEE / 978-1-4577-1546-4
By: Nagaraju, M.; Rakesh, M.;

Static Rate-Optimal Scheduling of Multirate DSP Algorithms via Retiming and Unfolding

2012 / IEEE / 978-1-4673-0883-0
By: Basten, T.; Geilen, M.; Xue-Yang Zhu; Stuijk, S.;

Unrolling and retiming of stream applications onto embedded multicore processors

2012 / IEEE / 978-1-4503-1199-1
By: Chatha, K.S.; Weijia Che;

FPGA implementation of retimed low power and high throughput DCT core using NEDA

2013 / IEEE
By: Mankar, Abhishek; Das, Ansuman Diptisankar; Prasad, N;

Relax-and-Retime: A methodology for energy-efficient recovery based design

2013 / IEEE
By: Parandhaman, Adithya; Venkataramani, Swagath; Ramasubramanian, Shankar Ganesh; Raghunathan, Anand;

Geometric Programming Formulation for Gate Sizing with Pipelining Constraints

2015 / IEEE
By: Naidu, Srinath R.;

Retiming for Delay Recovery After DfT Insertion on Interdie Paths in 3-D ICs

2014 / IEEE
By: Noia, B.; Chakrabarty, K.;

Algorithm transformation techniques for concurrent processors

1989 / IEEE
By: Parhi, K.K.;

Retiming and resynthesis: optimizing sequential networks with combinational techniques

1991 / IEEE
By: Brayton, R.K.; Sentovich, E.M.; Malik, S.; Sangiovanni-Vincentelli, A.;

Partitioning sequential circuits for logic optimization

1991 / IEEE / 0-8186-2270-9
By: Dey, S.; Kedem, G.; Brglez, F.;

Implementation of systolic algorithms using pipelined functional units

1990 / IEEE / 0-8186-9089-5
By: Valero, M.; Llaberia, J.M.; Navarro, J.J.; Valero-Garcia, M.;

Unfolding and retiming for high-level DSP synthesis

1991 / IEEE / 0-7803-0050-5
By: Brown, A.P.; Lucke, L.E.; Parhi, K.K.;

Optimizing resource utilization using transformations

1991 / IEEE / 0-8186-2157-5
By: Potkonjak, M.; Rabaey, J.;

Retiming and resynthesis: optimizing sequential networks with combinational techniques

1990 / IEEE
By: Sangiovanni-Vincentelli, A.; Brayton, R.K.; Sentovich, E.M.; Malik, S.;

Flexible datapath compilation for Phideo

1991 / IEEE / 0-8186-2185-0
By: Lippens, P.E.R.; van Meerbergen, J.L.; McSweeney, B.T.; van der Werf, A.; Verhaegh, W.F.J.;

Scheduling of DSP programs onto multiprocessors for maximum throughput

1993 / IEEE
By: Hoang, P.D.; Rabaey, J.M.;

Hierarchical scheduling of DSP programs onto multiprocessors for maximum throughput

1992 / IEEE / 0-8186-2967-3
By: Phu Hoang; Rabaey, J.;

Rate-optimal static scheduling for DSP data-flow programs

1993 / IEEE / 0-8186-3430-8
By: Sha, E.H.-M.; Chao, L.-F.;

A compiler for multiprocessor DSP implementation

1992 / IEEE / 0-7803-0532-9
By: Rabaey, J.; Hoang, P.;

High level DSP synthesis using the MARS design system

1992 / IEEE / 0-7803-0593-0
By: Parhi, K.K.; Wang, C.-Y.;

Throughput optimized architectural synthesis

1993 / IEEE
By: Gebotys, C.H.;

Efficient systolic array for linear discriminant function classifier

1991 / IEEE / 0-8186-2141-9
By: Klass, F.;

Static scheduling of uniform nested loops

1993 / IEEE / 0-8186-3442-1
By: Sha, E.H.-M.; Chao, L.-F.;

Optimizing resource utilization using transformations

1994 / IEEE
By: Rabaey, J.; Potkonjak, M.;

Optimal mapping of DSP application to architectures

1993 / IEEE / 0-8186-3230-5
By: Gebotys, C.H.; Gebotys, R.J.;

Maximally fast and arbitrarily fast implementation of linear computations (circuit layout CAD)

1992 / IEEE / 0-8186-3010-8
By: Rabaey, J.; Potkonjak, M.;

Maximizing the throughput of high performance DSP applications using behavioral transformations

1994 / IEEE / 0-8186-5410-4
By: Rabaey, J.M.; Shan-Hsi Huang;

Communication sensitive rotation scheduling

1994 / IEEE / 0-8186-6565-3
By: Tongsima, S.; Sha, E.H.-M.; Passos, N.L.;

On retiming for FPGA logic module minimization

1994 / IEEE / 0-8186-6565-3
By: Chen, Y.P.; Wong, D.F.;

Retiming for the global optimization of synchronous sequential circuit

1994 / IEEE / 0-8186-6565-3
By: Kaminska, B.; Lejmi, S.; Wagneur, E.;

High-level DSP synthesis using concurrent transformations, scheduling, and allocation

1995 / IEEE
By: Parhi, K.K.; Ching-Yi Wang;

Automatic synthesis and the cost of testing

1994 / IEEE / 0-7803-1886-2
By: Marchok, T.E.; Mary, W.;

Testability implications of performance driven logic synthesis

1995 / IEEE
By: Rajski, J.; El-Maleh, A.; Marchok, T.E.; Maly, W.;

Restructuring of synchronous logic circuits

1993 / IEEE / 0-8186-3410-3
By: Lin, B.;

Functional verification for retiming and rebuffering optimization

1993 / IEEE / 0-8186-3410-3
By: Kostelijk, A.P.; van der Werf, A.;

Recent progress in amplified undersea systems

1995 / IEEE
By: Akiba, S.; Yamamoto, S.; Edagawa, N.; Taga, H.;

Resynthesis and retiming of synchronous sequential circuits

1993 / IEEE / 0-7803-1281-3
By: Kaminska, B.; Lejmi, S.; Wagneur, E.;

Synchronous performance and reliability improvement in pipelined ASICs

1994 / IEEE / 0-7803-2020-4
By: Friedman, E.G.; Soyata, T.;

Using HYPER to teach datapath design techniques in an ASIC design course

1994 / IEEE / 0-7803-2020-4
By: Reese, B.;

Retiming and clock skew for synchronous systems

1994 / IEEE / 0-7803-1915-X
By: Hsing-Mean Sha; Liang-Fang Chao;

Partitioning and retiming of multi-dimensional systems

1994 / IEEE / 0-7803-1915-X
By: Passos, N.L.; Bass, S.C.; Hsing-Mean Sha, E.;

Technology mapping for sequential circuits based on retiming techniques

1993 / IEEE / 0-8186-4350-1
By: Weinmann, U.; Rosenstiel, W.;

Synthesis for testability by sequential redundancy removal using retiming

1995 / IEEE / 0-8186-7079-7
By: Yotsuyanagi, H.; Kinoshita, K.; Kajihara, S.;

Analysis and reduction of glitches in synchronous networks

1995 / IEEE / 0-8186-7039-8
By: van Meerbergen, J.; Leijten, J.; Jess, J.;

High performance DSP software using data-flow graph transformations

1994 / IEEE / 0-8186-6405-3
By: Meyr, H.; Ritz, S.; Zivojnovic, V.;

On the derivation of parallel filter structures for adaptive eigenvalue and singular value decompositions

1995 / IEEE / 0-7803-2431-5
By: McWhirter, J.G.; Proudler, I.K.; Deprettere, E.; Moonen, M.;

Time-constrained loop pipelining

1995 / IEEE / 0-8186-7213-7
By: Cortadella, J.; Sanchez, F.;

Retiming-based partial scan

1996 / IEEE
By: Tragoudas, S.; Kagaris, D.;

Wideband lasers and receivers for lasercom applications

1995 / IEEE / 0-7803-2489-7
By: Oleski, P.J.; Jaeger, J.L.; Carlson, R.T.;

Test sequence compaction by reduced scan shift and retiming

1995 / IEEE / 0-8186-7129-7
By: Kinoshita, K.; Kajihara, S.; Higami, Y.;

Formal derivation of a systolic array for recursive least squares estimation

1996 / IEEE
By: Moonen, M.; McWhirter, J.G.; Proudler, I.K.; Hekstra, G.;

Does retiming affect redundancy in sequential circuits?

1996 / IEEE / 0-8186-7228-5
By: Bhattacharya, B.B.; Das, D.K.;

Retiming with logic duplication transformation: theory and an application to partial scan

1996 / IEEE / 0-8186-7228-5
By: Chakradhar, S.T.; Balakrishnan, A.;

Surprises in sequential redundancy identification

1996 / IEEE / 0-8186-7424-5
By: Iyer, M.A.; Abramovici, M.; Long, D.E.;

Retiming of synchronous circuits with variable topology

1995 / IEEE / 0-8186-6905-5
By: Bucher, R.; Simon, S.; Nossek, J.A.;

Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits

1995 / IEEE / 0-8186-7000-2
By: Ayari, B.; Kaminska, B.; Lejmi, S.;

On the performance of level-clocked circuits

1995 / IEEE / 0-8186-7074-9
By: Ebeling, C.; Lockyear, B.;

One-chip receiver IC for 2.4 Gb/s optical communication systems

1995 / IEEE / 0-7803-2584-2
By: Tatsumi, T.; Hashimoto, T.; Morikawa, T.; Sato, F.; Suzaki, T.; Soda, M.; Tezuka, H.; Tashiro, T.;

Monotonicity constraints on path delays for efficient retiming with localized clock skew and variable register delay

1995 / IEEE / 0-7803-2570-2
By: Friedman, E.G.; Soyata, T.; Mulligan, J.H., Jr.;

Systematic design of architectures for M-ary tree-structured filter banks

1995 / IEEE / 0-7803-2612-1
By: Denk, T.C.; Parhi, K.K.;

Concurrent timing optimization of latch-based digital systems

1995 / IEEE / 0-8186-7165-3
By: Wentai Liu; Hong-Yean Hsieh; Gray, C.T.; Cavin, R.K.;

Discrete-relaxation-based heuristic techniques for video algorithm/architecture matching and system level transformations

1995 / IEEE / 0-8186-7310-9
By: Potkonjak, M.;

An applicative framework for video-rate systems programming

1995 / IEEE / 0-8186-7370-2
By: Phoukas, D.; Jullien, G.A.;

Overcoming chip-to-chip delays and clock skews

1996 / IEEE / 0-8186-7542-X
By: Even, G.; Litman, A.;

Hardware/software co-design for DSP applications via the HMS framework

1996 / IEEE / 0-7803-3192-3
By: Sha, E.H.-M.; Sheliga, M.;

The complexity of generalized retiming problems

1996 / IEEE
By: Verhaegh, W.F.J.; Korst, J.H.M.; Aarts, E.H.L.; de Fluiter, B.; van der Werf, A.;

Area efficient pipelined pseudo-exhaustive testing with retiming

1996 / IEEE / 0-7803-3294-6
By: Chung-Kuan Cheng; Ting-Ting Y. Lin; Huoy-Yu Liu;

Optimal clock period FPGA technology mapping for sequential circuits

1996 / IEEE / 0-7803-3294-6
By: Peichen Pan; Liu, C.L.;

On retiming of multirate DSP algorithms

1996 / IEEE / 0-7803-3192-3
By: Zivojnovic, V.; Schoenen, R.;

An ATPG-based framework for verifying sequential equivalence

1996 / IEEE / 0-7803-3541-4
By: Shi-Yu Huang; Glaeser, U.; Kuang-Chien Chen; Kwang-Ting Cheng;

Data flow partitioning with clock period and latency constraints

1997 / IEEE
By: Chung-Kuan Cheng; Lillis, J.; Shih, M.; Lung-Tien Liu;

An improved algorithm for performance optimal technology mapping with retiming in LUT-based FPGA design

1996 / IEEE / 0-8186-7554-3
By: Wu, C.; Cong, J.;

Metamorphosis: state assignment by retiming and re-encoding

1996 / IEEE / 0-8186-7597-7
By: Iyer, B.; Ciesielski, M.;

The case for retiming with explicit reset circuitry

1996 / IEEE / 0-8186-7597-7
By: Malik, S.; Singhal, V.; Brayton, R.K.;

Configurable spare processors: a new approach to system level fault-tolerance

1996 / IEEE / 0-8186-7545-4
By: Potkonjak, M.; Karri, R.; Kim, K.;

The practical application of retiming to the design of high-performance systems

1993 / IEEE / 0-8186-4490-7
By: Ebeling, C.; Lockyear, B.;

Performance-driven partitioning using retiming and replication

1993 / IEEE / 0-8186-4490-7
By: Ku, W.; Cheng, C.-K.; Chou, N.-C.; Shih, M.; Liu, L.-T.;

A constructive approach towards correctness of synthesis-application within retiming

1997 / IEEE / 0-8186-7786-4
By: Kumar, R.; Eisenbiegler, D.; Blumenrohr, C.;

SDH 10 Gb/s regenerator framer in 0.6 /spl mu/m CMOS

1997 / IEEE / 0-7803-3721-2
By: Rudberg, B.; Edman, A.;

Rotation scheduling: a loop pipelining algorithm

1997 / IEEE
By: LaPaugh, A.S.; Liang-Fang Chao; Sha, E.H.-M.;

A strategy for determining a Jacobi specific dataflow processor

1997 / IEEE / 0-8186-7959-X
By: Jun Ma; Deprettere, E.F.; Hekstra, G.; Rijpkema, E.;

Optimal placement of registers in data paths for low power design

1997 / IEEE / 0-7803-3583-X
By: Schimpfle, C.V.; Nossek, J.A.; Simon, S.;

Optimal clock period clustering for sequential circuits with retiming

1997 / IEEE / 0-8186-8206-X
By: Peichen Pan; Karandikar, A.K.; Liu, C.L.;

Scheduling data-flow graphs via retiming and unfolding

1997 / IEEE
By: Hsing-Mean Sha, E.; Liang-Fang Chao;

40 Gb/s WDM cross-connect with an electronic switching core: preliminary results from the WEST Consortium

1997 / IEEE / 0-7803-3895-2
By: Beccue, S.M.; Wu, D.; Meeker, D.; Campana, A.D.; Price, A.; Pedrotti, K.D.; Chang, C.E.; Bowers, J.; Zhang, S.Z.; Swass, M.; Kwong, N.; Huff, D.; Asbeck, P.M.; Metzger, A.; Wang, K.C.;

Retiming edge-triggered circuits under general delay models

1997 / IEEE
By: Lalgudi, K.N.; Papaefthymiou, M.C.;

MDG-based verification by retiming and combinational transformations

1998 / IEEE / 0-8186-8409-7
By: Mohamed, O.A.; Song, X.; Cerny, E.;

Improving the throughput of flexible-precision DSPS via algorithm transformation

1998 / IEEE / 0-7803-4428-6
By: Aggarwal, M.; Ahuja, N.; Shanbhag, N.;

Exhaustive scheduling and retiming of digital signal processing systems

1998 / IEEE
By: Parhi, K.K.; Denk, T.C.;

Optimal clock period clustering for sequential circuits with retiming

1998 / IEEE
By: Liu, C.L.; Karandikar, A.K.; Pan, P.;

Graph transformation for communication minimization using retiming

1998 / IEEE / 0-7803-4455-3
By: Sheliga, M.; Sha, E.H.-M.; Fei Chen; Zhihong Yu;

FPGA mapping of sequential circuits with retiming

1998 / IEEE / 0-7803-4455-3
By: Shragowitz, E.; Jun-Yong Lee;

Synthesis of folded multi-dimensional DSP systems

1998 / IEEE / 0-7803-4455-3
By: Sundararajan, V.; Parhi, K.K.;

Low power logic synthesis under a general delay model

1998 / IEEE / 1-58113-059-7
By: Narayanan, U.; Liu, C.L.; Peichen Pan;

Next Page