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Topic: Reconfigurable Architectures

Results

Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI

2011 / IEEE
By: Sejnowski, T.J.; Yu, T.; Cauwenberghs, G.;

Guest Editorial Special Section on Embedded Reconfigurable Computing Systems

2011 / IEEE
By: Ferrandi, F.; Kastner, R.; Lysaght, P.;

Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips

2011 / IEEE
By: Usami, K.; Nakamura, H.; Amano, H.; Kimura, M.; Ikebuchi, D.; Namiki, M.; Yasuda, Y.; Ozaki, N.; Saito, Y.; Kondo, M.;

High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures

2011 / IEEE
By: Doosan Cho; Yoon, J.W.; Shrivastava, A.; Jongeun Lee; Yongjoo Kim; Yunheung Paek;

Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation

2011 / IEEE
By: Coole, J.; Stitt, G.;

Data Archival to SD Card Via Hardware Description Language

2011 / IEEE
By: Todakar, V.S.; Elkeelany, O.;

Reconfigurable SoC-Based Smart Sensor for Wavelet and Wavelet Packet Analysis

2012 / IEEE
By: Cabal-Yepez, E.; Pena-Anaya, M.; Romero-Troncoso, R.J.; Osornio-Rios, R.A.; Garcia-Perez, A.;

Benefits of implementing a dynamic impairment-aware optical network: results of EU Project DICONET

2012 / IEEE
By: Manousakis, K.; Kokkinos, P.; Spadaro, S.; Careglio, D.; Perello, J.; Tomkos, I.; Azodolmolky, S.; Angelou, M.; Yabin Ye; Gagnaire, M.; Saradhi, C.V.; Colle, D.; Staessens, D.; Varvarigos, E.;

Reconfigurable Dual-Channel Multiband RF Receiver for GPS/Galileo/BD-2 Systems

2012 / IEEE
By: Jianjun Zhou; Tingting Mo; Jing Jin; Peichen Jiang; Wenjie Pan; Dongpo Chen;

Digital System for Acquisition and Processing of Detected Images

2012 / IEEE
By: Geraci, A.; Fiorini, C.; Abba, A.;

A Multifunctional Reconfigurable Pixeled Antenna Using MEMS Technology on Printed Circuit Board

2011 / IEEE
By: De Flaviis, F.; Besoli, A.G.;

Efficient Mapping of Task Graphs onto Reconfigurable Hardware Using Architectural Variants

2012 / IEEE
By: Bakhouya, M.; Narayana, V.K.; Miaoqing Huang; El-Ghazawi, T.; Gaber, J.;

MRTP: Mobile Ray Tracing Processor With Reconfigurable Stream Multi-Processors for High Datapath Utilization

2012 / IEEE
By: Lee-Sup Kim; Young-Jun Kim; Hong-Yun Kim;

A Reconfigurable Patch Antenna Using Liquid Metal Embedded in a Silicone Substrate

2011 / IEEE
By: Vaughan, R.G.; Menon, C.; Mahanfar, A.; Xing Jie Jiang; Mazlouman, S.J.;

Dynamic Variability in Software-Intensive Embedded System Families

2012 / IEEE
By: Capilla, R.; Bosch, J.;

Direct Baseband I-Q Regeneration Method for Five-Port Receivers Improving DC-Offset and Second-Order Intermodulation Distortion Rejection

2012 / IEEE
By: Burgos-Garcia, M.; Mbaye, A.; Huyart, B.; Mabrouk, K.; de la Morena-Alvarez-Palencia, C.;

Tackling Resource Variations Through Adaptive Multicore Execution Frameworks

2012 / IEEE
By: Orailoglu, A.; Chengmo Yang;

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays

2012 / IEEE
By: Pozzi, L.; Tanimura, K.; Ansaloni, G.; Dutt, N.;

Comparison of Preemption Schemes for Partially Reconfigurable FPGAs

2012 / IEEE
By: Edahiro, M.; Tomiyama, H.; Jozwik, K.; Takada, H.; Honda, S.;

Integrated route selection, transponder placement, wavelength assignment, and restoration in an advanced ROADM architecture

2012 / IEEE
By: Strand, J.L.;

The Load as an Energy Asset in a Distributed DC SmartGrid Architecture

2012 / IEEE
By: Balog, R.S.; Krein, P.T.; Weaver, W.W.;

Compiler-Assisted Data Distribution and Network Configuration for Chip Multiprocessors

2012 / IEEE
By: Melhem, R.; Abousamra, A.; Yong Li; Jones, A.K.;

A reconfigurable and programmable FPGA-based system for nonstandard ultrasound methods

2012 / IEEE
By: Housden, J.; Ricci, S.; Ramalli, A.; Guidi, F.; Tortoli, P.; Bassi, L.; Boni, E.; Dallai, A.;

A Synchronized Signaling Insertion and Detection Scheme for Reconfigurable Optical OFDM Access Networks

2012 / IEEE
By: Li, F.; Cao, Z.; Koonen, A.M.J.; Chen, L.; van den Boom, H.P.A.; Okonkwo, C.M.; Tang, J.; Tang, Q.; Tangdiongga, E.; Yu, J.;

Practical and Cost-Effective Bias Line Implementations for Reconfigurable Antennas

2012 / IEEE
By: Rahmat-Samii, Y.; Rajagopalan, H.; Kovitz, J. M.;

Programming Time-Multiplexed Reconfigurable Hardware Using a Scalable Neuromorphic Compiler

2012 / IEEE
By: Minkovich, K.; Nogin, A.; Youngkwan Cho; Cruz-Albrecht, J.M.; Srinivasa, N.;

Reconfigurable Sensing Antenna: A Slotted Patch Design With Temperature Sensation

2012 / IEEE
By: Qiao, Q.; Yang, F.; Sydanheimo, L.; Ukkonen, L.; Elsherbeni, A. Z.; Virtanen, J.;

Electronically Controlled Phasing Element for Single-Layer Reconfigurable Reflectarray

2012 / IEEE
By: Abbosh, A.; Li, Y.;

Implementation of Wireless Vision Sensor Node for Characterization of Particles in Fluids

2012 / IEEE
By: Khursheed, K.; Imran, M.; Ahmad, N.; O'Nils, M.; Lawal, N.;

Reconfigurable Photonic Feed for Sinuous Antenna

2012 / IEEE
By: Mitchell, A.; Lara, E.R.L.; Sarkhosh, N.; Emami, H.;

An Overview of Tuning Techniques for Frequency-Agile Antennas

2012 / IEEE
By: Petosa, A.;

SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-Power SRAMs

2012 / IEEE
By: Wei Zhang; Ting-Jung Lin; Jha, N.K.;

On an Improved FPGA Implementation of CNN-Based Gabor-Type Filters

2012 / IEEE
By: Tavsanoglu, V.; Yildiz, N.; Cesur, E.;

VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter

2012 / IEEE
By: Darwazeh, I.; Isam, S.; Perrett, M.R.; Whatmough, P.N.;

A dynamic reconfiguration approach for accelerating highly defective processors

2009 / IEEE / 978-1-4577-0236-5
By: Pereira, M.M.; Carro, L.;

GenerateRCS: A high-level design tool for generating reconfigurable computing systems

2009 / IEEE / 978-1-4577-0236-5
By: Becker, J.; Luhmann, J.; Gohringer, D.;

Proposal of instruction level modeling for Dynamically Reconfigurable Processor using SystemC

2009 / IEEE / 978-1-4577-0236-5
By: Kitamichi, J.;

Implementation of a reprogrammable DSP/FPGA based platform for real-time HD video coding

2010 / IEEE / 978-0-9552047-4-6
By: Frescura, F.; Baruffa, G.; Micanti, P.; Verducci, L.; Fiorucci, F.;

Architectural topologies for NoC datapath polymorphic processors

2011 / IEEE / 978-1-61284-466-4
By: Oruklu, E.; Weber, J.; Saniie, J.;

Reconfigurable architectures for silicon Physical Unclonable Functions

2011 / IEEE / 978-1-61284-466-4
By: Lao, Y.; Parhi, K.K.;

Energy reductions for embedded processors in reconfigurable hardware

2011 / IEEE / 978-1-61284-466-4
By: Hasan, M.Z.; Bird, M.;

Enforcing architectural contracts in high-level synthesis

2011 / IEEE / 978-1-4503-0636-2
By: Patil, N.; Chiou, D.; Bansal, A.;

Automated mapping for reconfigurable single-electron transistor arrays

2011 / IEEE / 978-1-4503-0636-2
By: Datta, S.; Chun-Yao Wang; Eachempati, S.; Yung-Chih Chen; Narayanan, V.; Yuan Xie;

A prototyping environment for high performance reconfigurable computing

2011 / IEEE / 978-1-4577-0642-4
By: Ben Atitallah, R.; Afonso, G.; Rubio, M.; Belanger, N.; Dekeyser, J.-L.; Loyer, A.;

Dataflow programming model for reconfigurable computing

2011 / IEEE / 978-1-4577-0642-4
By: Khiar, A.; Gantel, L.; Kessal, L.; Lemonnier, F.; Benkhelifa, A.; Miramond, B.;

A reconfigurable fabric supporting full C/C++ input

2011 / IEEE / 978-1-4577-0642-4
By: Portal, J.V.; Itturriet, F.P.; Rutzig, M.B.; Junqueira, A.A.; Carro, L.;

A dependable and dynamic network on chip suitable for FPGA-based reconfigurable systems

2011 / IEEE / 978-1-4577-0642-4
By: Tanougast, C.; Killian, C.; Toumi, S.; Frihi, M.; Dandache, A.;

Accelerating Computations on FPGA Carry Chains by Operand Compaction

2011 / IEEE / 978-1-4244-9457-6
By: Preusser, T.B.; Spallek, R.G.; Zabel, M.;

Built-In-Self-Test Methodology for Hardwares of Dynamically Reconfigurable Computer

2011 / IEEE / 978-1-4577-0856-5
By: Su Chen; Xiaojun Fu; Yongle Xie; Qizhong Zhou;

Virtualization of heterogeneous machines

2011 / IEEE / 978-1-4503-0636-2
By: Shukla, S.; Rabbah, R.; Cheng, P.; Bacon, D.F.; Auerbach, J.;

A Fault-Tolerant NoC Scheme using bidirectional channel

2011 / IEEE / 978-1-4503-0636-2
By: Yu-Hen Hu; Sao-Jie Chen; Deng-Yuan Zheng; Wen-Chung Tsai;

Dynamic binary translation to a reconfigurable target for on-the-fly acceleration

2011 / IEEE / 978-1-4503-0636-2
By: Kinsman, P.; Nicolici, N.;

Towards a power and energy efficient use of partial dynamic reconfiguration

2011 / IEEE / 978-1-4577-0642-4
By: Bilavarn, S.; Sentieys, O.; Chillet, D.; Bonamy, R.;

Runtime extraction of memory access information from the application source code

2011 / IEEE / 978-1-61284-383-4
By: Corina, M.; Ostadzadeh, S.A.; Bertels, K.; Galuzzi, C.;

Shared reconfigurable fabric for multi-core customization

2011 / IEEE / 978-1-4503-0636-2
By: Liang Chen; Mitra, T.;

Discrete cosine transform(DCT)-based reconfigurable system design

2011 / IEEE / 978-1-61284-466-4
By: Alluru, M.; Yufeng Lu; In Soo Ahn;

RecoNoC: A reconfigurable network-on-chip

2011 / IEEE / 978-1-4577-0642-4
By: Farisi, B.A.; Vancayseele, R.; Stroobandt, D.; Bruneel, K.; Heirman, W.;

Runtime Reconfigurable MPSoC architecture for control drive system

2011 / IEEE / 978-1-4244-9312-8
By: Ben Salem, A.K.; Ben Othman, S.; Abdelkrim, H.; Ben Saoud, S.;

Parallel template matching operations on a dynamically reconfigurable vision-chip architecture

2011 / IEEE / 978-1-61284-137-3
By: Nakada, H.; Kawahito, S.; Watanabe, M.;

Re²DA: Reliable and reconfigurable dynamic architecture

2011 / IEEE / 978-1-4577-0642-4
By: Hung-Manh Pham; Pillement, S.; Devaux, L.;

Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach

2011 / IEEE / 978-1-4577-0642-4
By: Castro, F.; Corbetta, S.; Zaccaria, V.; Palermo, G.; Agosta, G.; Reghizzi, S.C.; Fornaciari, W.; Silvano, C.; Bellasi, P.; Vanthournout, B.; Mahonen, P.; Ansari, J.; Ascheid, G.; Kempf, T.; Soudris, D.; Bartzas, A.; Anagnostopoulos, I.; Ykman-Couvreur, C.; Raghavan, P.; Palkovic, M.; Brandenburg, J.; Stabernack, B.; Hubert, H.; Zins, J.M.; Melpignano, D.; Speziale, E.;

Achieving hardware security for reconfigurable systems on chip by a proof-carrying code approach

2011 / IEEE / 978-1-4577-0642-4
By: Platzner, M.; Drzevitzky, S.;

Enhancing learning of digital systems using a remote FPGA lab

2011 / IEEE / 978-1-4577-0642-4
By: Morgan, F.; Cawley, S.;

Fast prototyping environment for embedded reconfigurable units

2011 / IEEE / 978-1-4577-0642-4
By: Lagadec, L.; Picard, D.;

Evaluation of speculative execution techniques for high-level language to hardware compilation

2011 / IEEE / 978-1-4577-0642-4
By: Koch, A.; Huthmann, J.; Thielmann, B.;

Runtime-datapath-remapping for fault-tolerant coarse-grained reconfigurable architectures

2011 / IEEE / 978-1-4577-0642-4
By: Rosenstiel, W.; Kuhn, T.; Schweizer, T.; Kuster, A.; Eisenhardt, S.;

Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systems

2011 / IEEE / 978-1-4577-0642-4
By: Samman, F.A.; Glesner, M.; Surapong, P.;

Fault containment in a reconfigurable Multi-Processor System-on-a-Chip

2011 / IEEE / 978-1-4244-9312-8
By: Hoftberger, O.; Obermaisser, R.;

RAW Introduction

2011 / IEEE / 978-1-61284-425-1
By: Cumplido, Rene; Benoit, Pascal; Becker, Juergen;

Test control&communication of hierarchical design-for-testability for testing dynamically reconfigurable computer

2011 / IEEE / 978-1-4577-0816-9
By: Tao Dai; Qi-zhong Zhou; Shu-yan Jiang; Yong-le Xie;

A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture

2011 / IEEE / 978-1-61284-425-1
By: Soudris, D.; Girardey, R.; Figuli, P.; Hubner, M.; Becker, J.; Siozios, K.;

A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors

2011 / IEEE / 978-1-61284-425-1
By: Becker, J.; Heisswolf, J.; Stripf, T.; Koenig, R.;

The research of cognitive communication networks

2011 / IEEE / 978-1-61284-486-2
By: Wu Wei;

High Speed Partial Run-Time Reconfiguration Using Enhanced ICAP Hard Macro

2011 / IEEE / 978-1-61284-425-1
By: Koch, D.; Hansen, S.G.; Torresen, J.;

Migrating Static Systems to Partially Reconfigurable Systems on Spartan-6 FPGAs

2011 / IEEE / 978-1-61284-425-1
By: Beckhoff, C.; Torresen, J.; Koch, D.;

ReBit: A Tool to Manage and Analyse FPGA-Based Reconfigurable Systems

2011 / IEEE / 978-1-61284-425-1
By: Sciuto, D.; Bonetto, A.; Cazzaniga, A.; Santambrogio, M.D.;

OpenPR: An Open-Source Partial-Reconfiguration Toolkit for Xilinx FPGAs

2011 / IEEE / 978-1-61284-425-1
By: Wood, A.; Frangieh, T.; Athanas, P.; Sohanghpurwala, A.A.;

Occam-pi as a High-Level Language for Coarse-Grained Reconfigurable Architectures

2011 / IEEE / 978-1-61284-425-1
By: ul Abdin, Z.; Svensson, B.;

LAPP: A Low Power Array Accelerator with Binary Compatibility

2011 / IEEE / 978-1-61284-425-1
By: Iwakami, T.; Devisetti, N.; Nakashima, Y.; Jun Yao; Nakada, T.; Yoshimura, K.;

Dynamic Reconfiguration for Irregular Code Using FNC-PAE Processor Cores

2011 / IEEE / 978-1-61284-425-1
By: Weinhardt, M.; May, F.; Vorbach, M.; Schuler, E.;

A Replacement Technique to Maximize Task Reuse in Reconfigurable Systems

2011 / IEEE / 978-1-61284-425-1
By: Mozos, D.; Clemente, J.A.; Resano, J.;

Just-in-Time Instruction Set Extension - Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture

2011 / IEEE / 978-1-61284-425-1
By: Grad, M.; Plessl, C.;

Enhancing Resource Utilization with Design Alternatives in Runtime Reconfigurable Systems

2011 / IEEE / 978-1-61284-425-1
By: Wold, A.; Torresen, J.; Koch, D.;

Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures

2011 / IEEE / 978-1-61284-425-1
By: Hemani, A.; Jafri, S.M.A.H.; Tenhunen, H.; Plosila, J.; Paul, K.;

Native Double Precision LINPACK Implementation on a Hybrid Reconfigurable CPU

2011 / IEEE / 978-1-61284-425-1
By: Thang Viet Huynh; Gansterer, W.N.; Mucke, M.;

On a Hybrid and General Control Scheme for Algorithms Represented as a Polytope

2011 / IEEE / 978-1-61284-425-1
By: Campos, J.M.; Cumplido, R.; Torres-Huitzil, C.; Perez-Andrade, R.;

A Multi-level Reconfigurable Architecture for a Wireless Sensor Node Coprocessing Unit

2011 / IEEE / 978-1-61284-425-1
By: Glesner, M.; Philipp, F.;

Reconfigurable Instruction Decoding for a Wide-Control-Word Processor

2011 / IEEE / 978-1-61284-425-1
By: Larsson-Edefors, P.; Sjalander, M.; Bardizbanyan, A.;

An architecture proposal of reconfigurable optical logic gates for BPSK signal

2011 / IEEE / 978-986-02-8974-9
By: Kawaguchi, Y.; Ishizaka, Y.; Koshiba, M.; Saitoh, K.;

The reconfigurable IP modules and design

2011 / IEEE / 978-1-61284-088-8
By: Xiao Luo; Limin Liu;

Design and verification on Openness and Reconfigurable Network Management Platform

2011 / IEEE / 978-1-61284-486-2
By: Mengnan Shi; Chuanhuang Li; Ligang Dong;

Research on the reconfigurable technique of SUAV flight control system

2011 / IEEE / 978-1-4244-9600-6
By: Fan Bing-xiao; Jiang Zhen; Xu Xin-li;

Optimal static scheduling of real-time dependent tasks on reconfigurable hardware devices

2011 / IEEE / 978-1-4244-9796-6
By: Belaid, I.; Benjemaa, M.; Muller, F.;

Hardware implementation on a Xilinx Virtex4

2011 / IEEE / 978-1-4244-9796-6
By: Maaref, H.; Halim, S.; Abdelaziz, A.; Aymen, M.;

Low power reconfigurable multiplier with reordering of partial products

2011 / IEEE / 978-1-61284-653-8
By: Balamurugan, S.; Sivanantham, S.; Kumar, M.V.P.; Mallick, P.S.;

Improving Reconfigurable Hardware Energy Efficiency and Robustness via DVFS-Scaled Homogeneous MP-SoC

2011 / IEEE / 978-1-61284-425-1
By: Nurmi, J.; Garzia, F.; Airoldi, R.;

Bitonic Sorting on Dynamically Reconfigurable Architectures

2011 / IEEE / 978-1-61284-425-1
By: Wanka, R.; Sibirko, E.; Angermeier, J.; Teich, J.;

Routing architecture and algorithms for a superconductivity circuits-based computing hardware

2011 / IEEE / 978-1-4244-9789-8
By: Mehdipour, F.; Murakami, K.; Inoue, K.; Kataoka, H.; Honda, H.;

Software Productivity of Field Experiments Using the Mobile Agents Open Architecture with Workflow Interoperability

2011 / IEEE / 978-1-4577-0713-1
By: Clancey, W.J.; Sierhuis, M.; Nado, R.; Lowry, M.;

Reconfigurable area and power efficient I-Q mapper for adaptive modulation

2011 / IEEE / 978-1-61284-857-0
By: Smitha, K.G.; Mahesh, R.; Vinod, A.P.;

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