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Topic: Phase Detectors

Results

Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS
2011 / IEEE
By: Eliezer, O.E.; Dulger, F.; Waheed, K.; Staszewski, R.B.;
An Exact Formula for the Pull-Out Frequency of a 2nd-Order Type II Phase Lock Loop
2011 / IEEE
By: Huque, A.-S.A.; Stensby, J.L.;
A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery
2011 / IEEE
By: Wenjing Yin; Hanumolu, P.K.; Young, B.; Talegaonkar, M.; Elshazly, A.; Inti, R.;
A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance
2011 / IEEE
By: Hanumolu, P.K.; Sasidhar, N.; Elshazly, A.; Yin, W.; Inti, R.;
Graphene Ambipolar Multiplier Phase Detector
2011 / IEEE
By: Rostami, M.; Guanxiong Liu; Xuebei Yang; Mohanram, K.; Balandin, A.A.;
An Interleaved, Interelement Phase-Detecting/Phase-Shifting Retrodirective Antenna Array for Interference Reduction
2011 / IEEE
By: Iwami, R.T.; Bao Jun Lei; Zamora, A.; Chun, T.F.; Shiroma, W.A.;
An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors
2012 / IEEE
By: Loke, A.L.S.; Doyle, B.A.; Maheshwari, S.K.; Fang, E.S.; Wang, C.L.; Tin Tin Wee; Fischette, D.M.;
A Waveform-Dependent Phase-Noise Analysis for Edge-Combining DLL Frequency Multipliers
2012 / IEEE
By: Shey-Shi Lu; Fang-Ren Liao;
A Frequency-Based Model for Limit Cycle and Spur Predictions in Bang-Bang All Digital PLL
2012 / IEEE
By: Burger, T.; Wei, J.; Helfenstein, M.; Basedau, P.; Dan Liu; Yangjian Chen;
A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector
2012 / IEEE
By: Yung Sern Tan; Kiat Seng Yeo; Chirn Chye Boon; Manh Anh Do;
Analytical Method for Computation of Phase-Detector Characteristic
2012 / IEEE
By: Yuldashev, R.V.; Yuldashev, M.V.; Kuznetsov, N.V.; Leonov, G.A.;
Detection of Human Beings in Motion Behind the Wall Using SAR Interferogram
2012 / IEEE
By: Zhimin Zhou; Qian Song; Biying Lu; Xiang Zhang;
A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme
2012 / IEEE
By: Kyu-Dong Hwang; Won-Young Lee; Lee-Sup Kim;
A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator
2012 / IEEE
By: Seong-Ook Jung; Dong-Hoon Jung; Kyungho Ryu;
A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation
2012 / IEEE
By: Lee-Sup Kim; Won-Young Lee;
Periodic Small Signal Analysis of a Wide Class of Type-II Phase Locked Loops Through an Exhaustive Variational Model
2012 / IEEE
By: Gajani, G.S.; Brambilla, A.; Bizzarri, F.;
Analytical methods for computation of phase-detector characteristics and PLL design
2011 / IEEE / 978-1-61284-943-0
By: Yuldashev, M.V.; Leonov, G.A.; Kuznetsov, N.V.; Yuldashev, R.V.;
The research of a novel matching demodulation system based on PZT
2011 / IEEE / 978-1-4577-0399-7
By: Liu Na; Li Jianxia; Liu Bo; Liang Wei;
Design of the battery resistance measurement system
2011 / IEEE / 978-1-4244-8161-3
By: Fu Yongjie; Yang Zhenji;
A phase detection scheme for clock and data recovery applications
2011 / IEEE / 978-1-4577-0618-9
By: Sanchez-Azqueta, C.; Celma, S.;
Design and implementation of charge-pump phase-locked loop
2011 / IEEE / 978-1-61284-463-3
By: Ming-Chia Hsieh; Min-Chin Lee; Ya-Ciou Lin;
Piecewise-linear phase frequency detector for fast-lock phase-locked loops
2011 / IEEE / 978-1-61284-857-0
By: Shuo-Hung Hsu; Jen-Ming Wu; Ching-Te Chiu; Jen-Chieh Chih; Yar-Sun Hsu;
Digital clock and data recovery circuit design: Challenges and tradeoffs
2011 / IEEE / 978-1-4577-0223-5
By: Hanumolu, P.K.; Inti, R.; Talegaonkar, M.;
32-nm SOI programmable, high-bandwidth 8.0-GHz digital PLL
2011 / IEEE / 978-1-4577-0223-5
By: Maheshwari, S.K.; Aggarwal, S.; Fang, E.;
Extraction algorithm of reflection coefficient for antenna VSWR meter based on directional coupler and integrated amplitude phase detector
2011 / IEEE / 978-1-4244-9793-5
By: Jisong Yang; Tao Huang;
The Design and Implementation of Configurable Symbol Synchronization Based on FPGA
2011 / IEEE / 978-1-4577-0676-9
By: Xuebo Jin; Jingjing Du; Shuiying Zhang; Guohong Yan;
Grid synchronization PLL robust to frequency variation, unbalanced and distorted voltage
2011 / IEEE / 978-1-4577-0541-0
By: Sanghoey Lee; Hanju Cha; Jeong-Hoon Lee;
Performance enhancement of direction finding for multiple baseline interferometry
2011 / IEEE / 978-89-93246-17-9
By: Kwag, Y.K.; Yang, H.J.;
A New Spectrum Sensing Circuit for Cognitive Radio Applications
2011 / IEEE / 978-1-4577-1797-0
By: Vahidpoor, Z.; Ahmadi, A.F.; Atlasbaf, Z.; Forooraghi, K.;
A leakage-current-recycling phase-locked loop in 65nm CMOS technology
2011 / IEEE / 978-1-4577-1785-7
By: Yun-Ta Tsai; I-Ting Lee; Shen-Iuan Liu;
A power-aware behavioral model of a five-state phase-frequency detector
2011 / IEEE / 978-0-85825-974-4
By: Weigel, R.; Fischer, G.; Glock, S.; Ussmueller, T.;
A multi-level phase detector in 90 nm CMOS
2012 / IEEE / 978-1-4673-1208-0
By: Sanchez-Azqueta, C.; Gimeno, C.; Celma, S.;
On the stability of DSP based P-I phase-locked loops containing matched filter delays
2011 / IEEE / 978-1-4673-0323-1
By: Farhang-Boroujeny, B.; Harris, F.;
Post silicon skew tuning: Survey and analysis
2012 / IEEE / 978-1-4673-0772-7
By: Hsuan-Ming Chou; Kun-Ting Tsai; Kao, M.Y.C.; Shih-Chieh Chang;
Design of an intrinsically-linear double-VCO-based ADC with 2nd-order noise shaping
2012 / IEEE / 978-1-4577-2145-8
By: Craninckx, J.; Xinpeng Xing; Peng Gao; Gielen, G.;
A novel phase detection system for linear all-digital phase locked loop
2012 / IEEE / 978-1-4673-0455-9
By: Sahoo, A.K.; Babu, B.C.; Dash, S.; Das, A.;
A novel digital GFSK demodulator for zero-IF receiver
2012 / IEEE / 978-1-4577-0345-4
By: Fengqi Yu; Lanqing Lu;
A Fast-Lock Analog Multiphase Delay-Locked Loop Using a Dual-Slope Technique
2012 / IEEE / 978-1-4673-0767-3
By: Han-Ying Liu; Chia-Chen Chang; Pin-Tseng Chen; Yu-Lung Lo;
An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery
2012 / IEEE / 978-0-7695-4688-9
By: Garside, J.D.; Plana, L.A.; Clark, D.M.; Temple, S.; Furber, S.B.;
A Medium-Range Hygrometer Using Nano-Porous Thin Film of $\gamma $ -$\hbox{Al}_{2} \hbox{O} _{3}$ With Electronics Phase Detection
2012 / IEEE
By: Saha, D.; Kumar, L.; Islam, T.; Sengupta, K.; Khan, S.A.;
Design of a digital multiradian phase detector and its application in fusion plasma interferometry
2010 / American Institute of Physics
By: A. Mlynek; G. Schramm; H. Eixenberger; G. Sips; K. McCormick; J. Eheberg; M. Zilker; K. Behler;
Wide-range harmonic lock detector with real-time delay measurement of delay-locked loop
2015 / IEEE
By: Hyoung, C.; Kim, S.; Park, K.;
Very high-sensitivity tunable phase detection of light power variations using electrical modulation of Si-photodiode in photovoltaic regime
2015 / IEEE
By: Janneh, M.; De Marcellis, A.; Palange, E.;
New phase and frequency detectors for carrier recovery in PSK and QAM systems
1988 / IEEE
By: Moridi, S.; Sari, H.;
Convergence time improvement in the carrier recovery circuits for digital QAM radio link
1989 / IEEE
By: Bernardini, A.; Parente, P.; De Fina, S.;
Designing on-chip clock generators
1992 / IEEE
By: Chen, D.-L.;
Interlace to progressive scan converter for IDTV
1992 / IEEE
By: Christopher, T.J.; Filliman, P.D.; Keen, R.T.;
Nonlinear analyses of a closed carrier recovery loop
1991 / IEEE / 0-87942-655-1
By: Bicman, B.; Jeran, D.; Petrovic, G.;
A multifunctional HBT technology
1990 / IEEE
By: Sullivan, G.J.; Nubling, R.B.; Wang, K.C.; Asbeck, P.M.; Higgins, J.A.; Sheng, N.H.; Chang, M.F.; Wang, N.L.; Ho, W.J.;
Environmental effects in mixers and frequency distribution systems
1992 / IEEE / 0-7803-0476-4
By: Walls, F.L.; Nelson, L.M.;
Phase and frequency detectors for clock synchronization in high-speed optical transmission systems
1992 / IEEE / 0-7803-0608-2
By: Sari, H.; Karam, G.; Houeix, H.;
Designing RF control subsystems using the VXIbus standard
1993 / IEEE / 0-7803-1203-1
By: Stepp, J.D.; Bridges, J.F.; Vong, F.C.;
Multi-level decision feedback equalization: an efficient realization of FDTS/DF
1995 / IEEE
By: Wood, R.; Kenney, J.G.;
Dynamic characterization of optical microwave transducers
1995 / IEEE / 0-7803-2581-8
By: Hilt, A.; Cabon, B.; Berceli, T.; Tedjini, S.; Pic, E.; Quoc, A.H.;
A performance comparison of 16 QAM digital PLL based demodulators
1994 / IEEE / 0-7803-1820-X
By: Fitz, M.P.; Chen, A.Y.; Sethare, W.A.;
Two phase detectors for 2.5-10 Gb/s NRZ data operation: a Hogge and a balanced mixer
1996 / IEEE / 0-7803-3504-X
By: Wang, K.C.; Price, A.; Penney, J.; Pedrotti, K.; Wu, D.Y.; Beccue, S.; Meeker, D.; Yen, A.C.;
A decision circuit with phase detectors for 10 Gb/s optical communication systems
1994 / IEEE / 0-7803-1975-3
By: Shikata, M.; Ushikubo, T.; Nishi, S.; Fujishiro, H.I.; Shigemasa, R.; Nishino, A.;
A 6 Gbps CMOS phase detecting DEMUX module using half-frequency clock
1998 / IEEE / 0-7803-4766-8
By: Abiko, H.; Fukaishi, M.; Nakamura, K.; Yotsuyanagi, M.; Matsumoto, A.;
A high resolution phase and frequency offset generator
1998 / IEEE / 0-7803-4373-5
By: Ascarrunz, F.G.;
The discrete wavelet transform as a tool for automatic phase pickers
1998 / IEEE / 0-7803-5073-1
By: Ooninex, P.;
On the performance of a low complexity baseband 2nd order delay locked loop incorporating a non-linear NCO
1998 / IEEE / 0-7803-4281-X
By: Sabel, L.;
A two-channel optical downconverter for phase detection
1998 / IEEE
By: Biernacki, P.D.; Esman, R.D.; Williams, K.J.; Enders, D.G.; Nichols, L.T.;
Low-power dividerless frequency synthesis using aperture phase detection
1998 / IEEE
By: Horowitz, M.A.; Eddleman, D.J.; Yue, C.P.; Min Xu; del Mar Hershenson, M.; Lee, T.H.; Samavati, H.; Mohan, S.S.; Shaeffer, D.K.; Shahani, A.R.; Rategh, H.R.;
Integrated set of instruments for transmission's performance measurements in radar systems
1998 / IEEE / 83-906662-0-0
By: Jasinski, E.; Darlak, J.;
Nonlinear distortion model for VCO-PLL FM transmission systems
1999 / IEEE
By: Pedro, J.C.; Madureira, R.C.; Carvalho, N.B.;
An auto-ranging 50-210 Mb/s clock recovery circuit with a time-to-digital converter
1999 / IEEE / 0-7803-5126-6
By: Wonchan Kim; Joonbae Park;
A 3.3 V high speed dual looped CMOS PLL with wide input locking range
1998 / IEEE / 0-8186-8914-5
By: Kwang Sub Yoon; Hyuk-Jun Sung; Hong Ki Min;
A high speed and low power phase-frequency detector and charge-pump
1999 / IEEE / 0-7803-5012-X
By: Won-Hyo Lee; Jun-Dong Cho; Sung-Dae Lee;
Free false lock and timing recovery independent frequency detector
1999 / IEEE / 0-7803-5284-X
By: Lozhkin, A.N.;
A new topology of controlled C/sup 3/A differentiator for multi-Gb/s optical applications
1999 / IEEE / 0-7803-5510-5
By: Centurelli, F.; Tommasino, P.; Trifiletti, A.;
InP-based MMIC components for an optical phase-locked loop
1999 / IEEE
By: Kao-Chih Syao; Yang, K.; Eisele, H.; Goetz, P.G.; Bhattacharya, P.; Qasaimeh, O.;
A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells
1999 / IEEE / 0-7803-5443-5
By: Jongsang Choi; Yongsam Moon; Min-Kyu Kim; Deog-Kyoon Jeong; Kyeongho Lee;
High performance analog and digital PLL design
1999 / IEEE / 0-7803-5471-0
By: Almeida, T.M.; Piedade, M.S.;
Dead-zone-less PLL frequency synthesizer by hybrid phase detectors
1999 / IEEE / 0-7803-5471-0
By: Matsuda, Y.; Ishii, H.; Furuhashi, R.; Kitai, N.; Obote, S.; Sumi, Y.; Fukui, Y.;
A radiation-hard 80 MHz phase locked loop for clock and data recovery
1999 / IEEE / 0-7803-5471-0
By: Toifl, T.; Moreira, P.;
A monolithic 1.25 Gbits/sec CMOS clock/data recovery circuit for fibre channel transceiver
1999 / IEEE / 0-7803-5471-0
By: Chen, H.; Wu, L.; Black, W.; Lee, E.; Geiger, R.; Nagavarapu, S.;
Measuring phase noise at K-hand
1999 / IEEE / 0-7803-5425-7
By: Chut-San Tsang; Key-Bolotin, J.A.;
An integrated CDMA intermediate-frequency transceiver for wireless local loop
1999 / IEEE
By: Jae-Heon Lee; Ho-Jun Song; Hye-Ju Seo;
PLL synthesizer with multi-programmable divider and multi-phase detector
1999 / IEEE
By: Sumi, Y.; Furuhashi, R.; Ishii, H.; Kitai, N.; Obote, S.;
SiGe clock and data recovery IC with linear type PLL for 10 Gb/s SONET application
1999 / IEEE / 0-7803-5712-4
By: Greshishchev, Y.M.; Schvan, P.;
Soft-decision phase detection with Viterbi decoding for CPM signals
1999 / IEEE
By: Fonseka, J.P.;
An integrated programmable low-noise charge pump
1999 / IEEE / 0-7803-5682-9
By: Rahkonen, T.; Hakkinen, J.; Kostamovaara, J.;
Analysis of parameter-independent PLLs with bang-bang phase-detectors
1998 / IEEE / 0-7803-5008-1
By: Moreira, P.; Toifl, T.H.; Placidi, P.; Marchioro, A.;
Efficient clock recovery architecture
1998 / IEEE / 0-7803-5008-1
By: Mendez-Rivera, M.; Sanchez-Sinencio, E.; Silva-Martinez, J.; Valero-Lopez, A.;
Design considerations of sampled analog equalizer for hard-disk read channel
1999 / IEEE / 0-7803-5739-6
By: Jungryoul Choi; Joongho Choi;
Theoretical evaluation and simulation of a novel phase locked loop with low phase noise and fast settling times
1999 / IEEE / 0-7803-5546-6
By: De Villiers, J.P.; Linde, L.P.;
An integrated CDMA intermediate-frequency transceiver for 10-MHz wireless local loop
1999 / IEEE / 0-7803-5727-2
By: Jong-Moon Kim; Sang-Woo Hwang; Jae-Heon Lee; Ho-Jun Song;
A delay locked loop circuit with mixed-mode tuning
1999 / IEEE / 0-7803-5705-1
By: Jin-Ku Kang; Yeo-San Song;
A 3-cycle lock time delay-locked loop with a parallel phase detector for low power mobile systems
1999 / IEEE / 0-7803-5705-1
By: Miyazaki, M.; Ishibashi, K.;
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance
2000 / IEEE
By: Deog-Kyoon Jeong; Kyeongho Lee; Jongsang Choi; Yongsam Moon; Min-Kyu Kim;
Active GHz clock network using distributed PLLs
2000 / IEEE / 0-7803-5853-8
By: Chandrakasan, A.; Gutnik, V.;
A 1 GHz portable digital delay-locked loop with infinite phase capture ranges
2000 / IEEE / 0-7803-5853-8
By: Yamashida, H.; Sato, T.; Sumi, Y.; Matsushima, Y.; Yamashina, M.; Yamaguchi, H.; Mizuno, M.; Minami, K.; Nakano, T.;
A 0.18 /spl mu/m 256 Mb DDR-SDRAM with low-cost post-mold-tuning method for DLL replica
2000 / IEEE / 0-7803-5853-8
By: Mitsui, K.; Hamamoto, T.; Kikuda, S.; Furutani, K.; Kato, T.; Kuge, S.; Ozaki, H.; Konishi, Y.; Akiyama, M.; Nakaoka, Y.; Kawaguchi, Z.; Haraguchi, M.; Kubo, T.; Amano, T.; Kono, T.; Kawasaki, S.; Komiya, Y.; Hamade, K.; Setogawa, J.;
Automatic ultrasonic measurement of sound velocity in liquids by a phase-locked loop method
1999 / IEEE / 0-7803-5400-1
By: Ikeda, K.;
Correlation-based noise measurements below the thermal noise floor
1999 / IEEE / 0-7803-5400-1
By: Giordano, V.; Rubiola, E.;
Fully integrated 94-GHz subharmonic injection-locked PLL circuit
2000 / IEEE
By: Haydl, W.H.; Berceli, T.; Neumann, M.; Kudszus, S.;
2-dimensional audio phase measurements
2000 / IEEE / 0-7803-5890-2
By: Childs, J.; Daniel, J.; Schmalzel, J.; Cheung, D.; Shah, A.;
Comparison of carrier recovery techniques in M-QAM digital communication systems
2000 / IEEE / 0-7803-5957-7
By: Gagnon, F.; Mouaki Benani, A.;
A 10-Gb/s CMOS clock and data recovery circuit
2000 / IEEE / 0-7803-6309-4
By: Razavi, B.; Savoj, J.;
Frequency domain analysis of double sampling phase-locked loop
2000 / IEEE / 0-7803-5482-6
By: Frigyik, B.; Kolumban, G.; Kennedy, M.P.;

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