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Topic: Networks On Chips

Results

Low latency and energy efficient multicasting schemes for 3D NoC-based SoCs
2011 / IEEE / 978-1-4577-0170-2
By: Xiaohang Wang; Peng Liu; Huang, M.C.; Yingtao Jiang; Mei Yang; Palesi, M.;
Powering networks on chips
2001 / IEEE / 1-58113-418-5
By: De Micheli, G.; Benini, L.;
Networks on chips: a new SoC paradigm
2002 / IEEE
By: Benini, L.; De Micheli, G.;
A framework for security on NoC technologies
2003 / IEEE / 0-7695-1904-0
By: Gebotys, R.J.; Gebotys, C.H.;
An Application-Specific Design Methodology for STbus Crossbar Generation
2005 / IEEE / 0-7695-2288-2
By: De Micheli, G.; Murali, S.;
Performance driven reliable link design for networks on chips
2005 / IEEE / 0-7803-8736-8
By: Murali, S.; Tamhankar, R.R.; De Micheli, G.;
Formal methods for networks on chips
2005 / IEEE / 0-7695-2363-3
By: Goossens, K.;
On-chip networks
2005 / IEEE
By: Gupta, R.;
Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research
2005 / IEEE
By: Ivanov, A.; De Micheli, G.;
An approach that will NoC your SoCs off!
2005 / IEEE
By: Saleh, R.;
Traffic configuration for evaluating networks on chips
2005 / IEEE / 0-7695-2403-6
By: Zhonghai Lu; Jantsch, A.;
Mapping and configuration methods for multi-use-case networks on chips
2006 / IEEE / 0-7803-9451-8
By: Coenen, M.; Murali, S.; De Micheli, G.; Goossens, K.; Radulescu, A.;
Interconnect testing for networks on chips
2006 / IEEE / 0-7695-2514-8
By: Tragoudas, S.; Stewart, K.;
A Methodology for Mapping Multiple Use-Cases onto Networks on Chips
2006 / IEEE / 3-9810801-1-4
By: Coenen, M.; Srinivasan Murali; De Micheli, G.; Goossens, K.; Radulescu, A.;
Application Specific NoC Design
2006 / IEEE / 3-9810801-1-4
By: Benini, L.;
Networks on Chips for High-End Consumer-Electronics TV System Architectures
2006 / IEEE / 3-9810801-1-4
By: Duque, H.; Steenhof, F.; Llopis, R.P.; Goossens, K.; Nilsson, B.;
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips
2006 / IEEE / 3-901882-19-7
By: Raffo, L.; De Micheli, G.; Benini, L.; Carta, S.; Murali, S.; Angiolini, F.; Meloni, P.; Atienza, D.;
Designing Application-Specific Networks on Chips with Floorplan Information
2006 / IEEE / 1-59593-389-1
By: Raffo, L.; De Micheli, G.; Benini, L.; Carta, S.; Murali, S.; Angiolini, F.; Meloni, P.; Atienza, D.;
Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips
2006 / IEEE / 1-4244-0621-8
By: Pulling, A.; Angiolini, F.; Tamhankar, R.; Murali, S.; De Micheli, G.; Benini, L.; Atienza, D.;
An Efficient Clocking Scheme for On-Chip Communications
2006 / IEEE / 1-4244-0386-3
By: Bojnordi, M.N.; Madani, N.M.; Semsarzade, M.; Afzali-Kusha, A.;
An Information Theory Approach to Power - Optimal Trafic Routing in Networks on Chips
2007 / IEEE / 1-4244-0920-9
By: Sotiriadis, P.P.;
Synthesis of networks on chips for 3D systems on chips
2009 / IEEE / 978-1-4244-2748-2
By: Seiculescu, C.; Murali, S.; De Micheli, G.; Benini, L.;
An Outlook on Design Technologies for Future Integrated Systems
2009 / IEEE
By: De Micheli, G.;
Cascaded Microresonator-Based Matrix Switch for Silicon On-Chip Optical Interconnection
2009 / IEEE
By: Xianshu Luo; Poon, A.W.; Hui Chen; Fang Xu;
Adaptive routing using context-aware agents for networks on chips
2009 / IEEE / 978-1-4244-5750-2
By: Nickray, M.; Afzali-kusha, A.; Dehyadgari, M.;
Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion
2011 / IEEE / 978-1-61284-914-0
By: Wei Zhong; Goto, S.; Sheqin Dong; Yoshimura, T.; Song Chen; Bei Yu;
Cross clock-domain TDM virtual circuits for networks on chips
2011 / IEEE / 978-1-4503-0720-8
By: Zhonghai Lu;

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