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Topic: Network-on-chip

Results

A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip

2011 / IEEE
By: Wooyoung Jang; Pan, D.Z.;

Three-dimensional image processing VLSI system with network-on-chip system and reconfigurable memory architecture

2011 / IEEE
By: Yun Yang;

Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks

2011 / IEEE
By: Bergman, K.; Hendry, G.; Chan, J.; Carloni, L.P.;

CNoC: High-Radix Clos Network-on-Chip

2011 / IEEE
By: Chao, H.J.; Artan, N.S.; Ming Yang; Yu-Hsiang Kao;

Application-Aware NoC Design for Efficient SDRAM Access

2011 / IEEE
By: Pan, D.Z.; Wooyoung Jang;

Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm

2011 / IEEE
By: Jain, T.N.K.; Gwan Choi; Sprintson, A.; Gratz, P.V.; Ramakrishna, M.;

Dynamic Programming Networks for Large-Scale 3D Chip Integration

2011 / IEEE
By: Chi-Sang Poon; Yakovlev, A.; Yicong Meng; Kai-Pui Lam; Kuan Zhou; Al-Dujaily, R.; Mak, T.;

Low-Power, Real-Time Object-Recognition Processors for Mobile Vision Systems

2012 / IEEE
By: Kim, Joo-Young; Lee, Seungjin; Park, Junyoung; Hong, Injoon; Woo, Jeong-Ho; Oh, Jinwook; Kim, Gyeonghoon; Yoo, Hoi-Jun;

A 92-mW Real-Time Traffic Sign Recognition System With Robust Illumination Adaptation and Support Vector Machine

2012 / IEEE
By: Seungjin Lee; Jinwook Oh; Joonsoo Kwon; Junyoung Park; Hoi-Jun Yoo; Joo-Young Kim;

Real-Time Scheduling of Concurrent Transactions in Multidomain Ring Buses

2012 / IEEE
By: Pellizzoni, R.; Bui, B.D.; Caccamo, M.;

A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI

2012 / IEEE
By: Carloni, L.P.; Mantovani, P.; Warren, S.; Petracca, M.; Sturcken, N.; Shepard, K.L.; Peterchev, A.V.;

A QoS-Enabled On-Die Interconnect Fabric for Kilo-Node Chips

2012 / IEEE
By: Hestness, J.; Grot, B.; Mutlu, O.; Keckler, S.;

A Dynamically Adjusting Gracefully Degrading Link-Level Fault-Tolerant Mechanism for NoCs

2012 / IEEE
By: Vitkovskiy, A.; Nicopoulos, C.; Soteriou, V.;

A System-Level Modeling Methodology for Performance-Driven Component Selection in Multicore Architectures

2012 / IEEE
By: Khoshgoftaar, T.M.; Hamza-Lup, G.L.; Agarwal, A.;

HORNET: A Cycle-Level Multicore Simulator

2012 / IEEE
By: Keun Sup Shim; Myong Hyon Cho; Lis, M.; Pengju Ren; Fletcher, C.W.; Devadas, S.; Nanning Zheng; Khan, O.;

Noise Effects on Excitable Chaotic Attractors in Coupled Light-Emitting Diodes

2012 / IEEE
By: Meucci, R.; Al-Naimee, K.A.; Marino, F.; Ciszak, M.; Abdalah, S.F.; Arecchi, F.T.;

On the Impact of Within-Die Process Variation in GALS-Based NoC Performance

2012 / IEEE
By: Silla, F.; Roca, A.; Hernandez, C.; Duato, J.; Flich, J.;

Memory-Efficient On-Chip Network With Adaptive Interfaces

2012 / IEEE
By: Tenhunen, H.; Plosila, J.; Liljeberg, P.; Ebrahimi, M.; Daneshtalab, M.;

On-Chip Network-Enabled Multicore Platforms Targeting Maximum Likelihood Phylogeny Reconstruction

2012 / IEEE
By: Majumder, T.; Kalyanaraman, A.; Pande, P.P.; Borgens, M.E.;

Intelligent Hotspot Prediction for Network-on-Chip-Based Multicore Systems

2012 / IEEE
By: Kakoulli, E.; Theocharides, T.; Soteriou, V.;

A Reliable Routing Architecture and Algorithm for NoCs

2012 / IEEE
By: DeOrio, A.; Chen, G.; Jin Hu; Blaauw, D.; Sylvester, D.; Bertacco, V.; Fick, D.;

Power-efficient calibration and reconfiguration for optical network-on-chip

2012 / IEEE
By: Ming Gao; Lisherness, P.; Yan Zheng; Shiyuan Yang; Hong Wang; Kwang-Ting Cheng; Bovington, J.;

An Oblivious Routing Algorithm for 3D Mesh Networks to Achieve a New Worst-Case Throughput Bound

2012 / IEEE
By: Chia-Wei Chang; Guang Sun; Lieguang Zeng; Bill Lin;

Characterizing Vulnerability of Network Interfaces in Embedded Chip Multiprocessors

2012 / IEEE
By: Yi Xiang; Yong Zou; Pasricha, S.;

A Generic Optical Router Design for Photonic Network-on-Chips

2012 / IEEE
By: Jianyi Yang; Yingtao Jiang; Lei Zhang; Mei Yang; Xianfang Tan;

Compiler-Assisted Data Distribution and Network Configuration for Chip Multiprocessors

2012 / IEEE
By: Melhem, R.; Abousamra, A.; Yong Li; Jones, A.K.;

A Universal Method for Constructing N-Port Nonblocking Optical Router for Photonic Networks-On-Chip

2012 / IEEE
By: Ruiqiang Ji; Rui Min; Lin Yang; Lei Zhang; Qiaoshan Chen;

Adaptive-Tree Multicast: Efficient Multidestination Support for CMP Communication Substrate

2012 / IEEE
By: Menezo, L.G.; Puente, V.; Abad, P.; Angel Gregorio, J.;

Codesign of NoC and Cache Organization for Reducing Access Latency in Chip Multiprocessors

2012 / IEEE
By: Jones, A.K.; Abousamra, A.; Melhem, R.;

Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip

2012 / IEEE
By: Al-Dujaily, R.; Palesi, M.; Yakovlev, A.; Fei Xia; Mak, T.;

Low Latency and Energy Efficient Optical Network-on-Chip Using Wavelength Assignment

2012 / IEEE
By: Yintang Yang; Huaxi Gu; Zheng Chen; Ke Chen;

A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures

2012 / IEEE
By: Marek-Sadowska, M.; Nandakumar, V.S.;

Using Transmission Lines for Global On-Chip Communication

2012 / IEEE
By: Hui Wu; Huang, M.; Jie Xu; Jianyun Hu; Carpenter, A.; Peng Liu;

Swizzle-Switch Networks for Many-Core Systems

2012 / IEEE
By: Sylvester, D.; Wenisch, T.F.; Das, R.; Cieslak, M.; Blake, G.; Pinckney, N.; Blaauw, D.; Manville, T.; Dreslinski, R.G.; Sewell, K.; Satpathy, S.; Mudge, T.;

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

2012 / IEEE
By: Giovannini, P.; Beanato, G.; Leblebici, Y.; Temiz, Y.; Zervas, M.; Athanasopoulos, P.; Cevrero, A.;

Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges

2012 / IEEE
By: Ganguly, A.; Deb, S.; Deukhyoun Heo; Belzer, B.; Pande, P.P.;

Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput

2012 / IEEE
By: Plosila, J.; Tuuna, S.; Nigussie, E.; Tenhunen, H.; Isoaho, J.;

Investigating runtime task mapping for NoC-based multiprocessor SoCs

2009 / IEEE / 978-1-4577-0236-5
By: Carvalho, E.; Moraes, F.; Calazans, N.;

A Multi-objective Adaptive Immune Algorithm for NoC mapping

2009 / IEEE / 978-1-4577-0236-5
By: Strum, M.; Sepulveda, M.J.; Chau, W.J.;

Multi-path routing in time-division-multiplexed networks on chip

2009 / IEEE / 978-1-4577-0236-5
By: Stefan, R.; Goossens, K.;

Crosstalk fault tolerant NoC - Design and evaluation

2009 / IEEE / 978-1-4577-0236-5
By: Moraes, F.G.; Lucas, A.H.;

BrownPepper: A SystemC-based simulator for performance evaluation of Networks-on-Chip

2009 / IEEE / 978-1-4577-0236-5
By: Zeferino, C.A.; Pizzoni, M.R.; Bruch, J.V.;

Performance and energy evaluation of memory hierarchies in NoC-based MPSoCs under latency

2009 / IEEE / 978-1-4577-0236-5
By: Barcelos, D.; Girao, G.; Wagner, F.R.;

Managing QoS flows at task level in NoC-based MPSoCs

2009 / IEEE / 978-1-4577-0236-5
By: Carara, E.; Moraes, F.; Calazans, N.;

Highly efficient reconfigurable routers in Networks-on-Chip

2009 / IEEE / 978-1-4577-0236-5
By: Carro, L.; Concatto, C.; Matos, D.; Susin, A.; Kreutz, M.; Kastensmidt, F.;

A study on WK-recursive topology using gpNoCsim++ simulator and comparison to Other topologies

2009 / IEEE / 978-1-4577-0236-5
By: Ahrabi, A.A.A.; Bahrbegi, H.; Jamali, M.A.J.; Bahrbegi, M.;

Clocked and asynchronous FIFO characterization and comparison

2009 / IEEE / 978-1-4577-0236-5
By: HoSuk Han; Stevens, K.S.;

Planar adaptive fault-tolerant routing in PRDT(2,1)-based NoCs

2010 / IEEE / 978-1-4244-8598-7
By: Zhen Zhang; Xinming Duan;

Architectural topologies for NoC datapath polymorphic processors

2011 / IEEE / 978-1-61284-466-4
By: Oruklu, E.; Weber, J.; Saniie, J.;

DRAIN: Distributed Recovery Architecture for Inaccessible Nodes in multi-core chips

2011 / IEEE / 978-1-4503-0636-2
By: DeOrio, A.; Li-Shiuan Peh; Bertacco, V.; Aisopos, K.;

Evaluating the feasibility of network coding for NoCs

2011 / IEEE / 978-1-4577-0642-4
By: Indrusiak, L.S.;

Exploiting multicast messages in cache-coherence protocols for NoC-based MPSoCs

2011 / IEEE / 978-1-4577-0642-4
By: Moraes, F.G.; Carara, E.A.; Chaves, T.M.;

HeMPS-S: A homogeneous NoC-based MPSoCs framework prototyped in FPGAs

2011 / IEEE / 978-1-4577-0642-4
By: Biazi, A.; Wachter, E.W.; Moraes, F.G.;

Improving performance of NoCs by packet prioritization

2011 / IEEE / 978-1-61284-943-0
By: Mohandesi, M.; Mohandesi, E.;

Dynamic resource management in modern multicore SoCs by exposing NoC services

2011 / IEEE / 978-1-4577-0642-4
By: Coppola, M.; Kornaros, G.; Motakis, A.;

A dependable and dynamic network on chip suitable for FPGA-based reconfigurable systems

2011 / IEEE / 978-1-4577-0642-4
By: Tanougast, C.; Killian, C.; Toumi, S.; Frihi, M.; Dandache, A.;

High-performance on-chip network platform for memory-on-processor architectures

2011 / IEEE / 978-1-4577-0642-4
By: Daneshtalab, M.; Tenhunen, H.; Plosila, J.; Liljeberg, P.; Ebrahimi, M.;

A Fault-Tolerant NoC Scheme using bidirectional channel

2011 / IEEE / 978-1-4503-0636-2
By: Yu-Hen Hu; Sao-Jie Chen; Deng-Yuan Zheng; Wen-Chung Tsai;

Capacity optimized NoC for multi-mode SoC

2011 / IEEE / 978-1-4503-0636-2
By: Walter, I.; Kutten, S.; Cidon, I.; Kantor, E.;

A stochastic network calculus based approach for on-chip networks

2011 / IEEE / 978-988-17255-9-2
By: Chen Jin-Wen; Zhu Jin; Xi Hong-Sheng; Tang Liang;

Low power heterogeneous 3D Networks-on-Chip architectures

2011 / IEEE / 978-1-61284-383-4
By: Agyeman, M.O.; Shahrabi, A.; Ahmadinia, A.;

Abstraction-based performance verification of NoCs

2011 / IEEE / 978-1-4503-0636-2
By: Seshia, S.; Brady, B.; Holcomb, D.;

Loopback output router for reliable Network on Chip

2011 / IEEE / 978-1-4577-1056-8
By: Killian, C.; Dandache, A.; Monteiro, F.; Tanougast, C.;

2011 / IEEE / 978-1-61284-383-4
By: Alfaro, F.J.; Andujar, F.J.; Trivino, F.; Ros, A.; Sanchez, J.L.;

A deadlock-free fault-tolerant routing algorithm based on pseudo-receiving mechanism for Networks-on-Chip of CMP

2011 / IEEE / 978-1-61284-774-0
By: Jinwen Li; Lunguo Xie; Yancang Chen; Zhonghai Lu;

Slice router: For fine-granularity fault-tolerant Networks-on-Chip

2011 / IEEE / 978-1-61284-774-0
By: Zhonghai Lu; Jinwen Li; Lunguo Xie; Yancang Chen;

Wormhole routing optimization algorithm based on virtual channel switching

2011 / IEEE / 978-1-61284-774-0
By: Xiangxiang Zhang; Mingxiang Zang; Wen Jia;

RecoNoC: A reconfigurable network-on-chip

2011 / IEEE / 978-1-4577-0642-4
By: Farisi, B.A.; Vancayseele, R.; Stroobandt, D.; Bruneel, K.; Heirman, W.;

A reconfiguration technique for area-efficient network-on-chip topologies

2011 / IEEE / 978-1-4577-0139-9
By: Logvinenko, A.; Tutsch, D.;

Adaptive approach to tolerate multiple faulty links in Network-on-Chip

2011 / IEEE / 978-1-4577-1490-0
By: Kastensmidt, F.L.; Carro, L.; Concatto, C.; Kologeski, A.;

Invited paper: Design criteria for dependable System-on-Chip architectures

2011 / IEEE / 978-1-4577-0642-4
By: Ying, H.; Jaiswal, A.; Samman, F.A.; Hollstein, T.; Hofmann, K.; Glesner, M.;

NoCmodel: An extensible framework for Network-on-Chips modeling

2011 / IEEE / 978-1-4577-0642-4
By: Lazaro, J.; Zuloaga, A.; Astarloa, A.; Diaz, O.; Jimenez, J.;

Exploration of MPSoC monitoring and management systems

2011 / IEEE / 978-1-4577-0642-4
By: Daneshtalab, M.; Fattah, M.; Plosila, J.; Liljeberg, P.;

A suitable NoC switch for on-line routing fault detection

2011 / IEEE / 978-1-61284-137-3
By: Dandache, A.; Monteiro, F.; Tanougast, C.; Killian, C.;

A new mechanism to reduce congestion on TDM networks-on-chips

2011 / IEEE / 978-1-4577-0642-4
By: Legat, J.-D.; Lusala, A.K.; Vergeylen, D.;

Exploring heterogeneous NoC-based MPSoCs: From FPGA to high-level modeling

2011 / IEEE / 978-1-4577-0642-4
By: Ost, L.; Moraes, F.; Robert, M.; Indrusiak, L.S.; Mandelli, M.; Sassatelli, G.; Varyani, S.; Wachter, E.; Almeida, G.M.;

Simulations of NoC topologies for generalized hierarchical completely-connected networks

2011 / IEEE / 978-1-4577-0642-4
By: Takabatake, T.;

Efficient congestion-aware selection method for on-chip networks

2011 / IEEE / 978-1-4577-0642-4
By: Plosila, J.; Liljeberg, P.; Daneshtalab, M.; Ebrahimi, M.; Tenhunen, H.;

Intra- and inter-circuit network for Petri nets based components

2011 / IEEE / 978-1-4244-9312-8
By: Ferreira, R.; Gomes, L.; Costa, A.;

Fault containment in a reconfigurable Multi-Processor System-on-a-Chip

2011 / IEEE / 978-1-4244-9312-8
By: Hoftberger, O.; Obermaisser, R.;

Device modeling and system simulation of nanophotonic on-chip networks for reliability, power and performance

2011 / IEEE / 978-1-4503-0636-2
By: Li Shang; Mickelson, A.; Xi Chen; Mohamed, M.; Zheng Li;

Process variation-aware routing in NoC based multicores

2011 / IEEE / 978-1-4503-0636-2
By: Sharifi, A.; Kandemir, M.;

FlexiBuffer: Reducing leakage power in on-chip network routers

2011 / IEEE / 978-1-4503-0636-2
By: Sungjoo Yoo; Kim, J.; Gwangsun Kim;

A 98 GMACs/W 32-core vector processor in 65nm CMOS

2011 / IEEE / 978-1-61284-660-6
By: Xun He; Goto, S.; Xin Jin; Dajiang Zhou;

A NoC Traffic Suite Based on Real Applications

2011 / IEEE / 978-1-4577-0803-9
By: Weichen Liu; Zhehui Wang; Nikdast, M.; Wei Zhang; Jiang Xu; Xuan Wang; Yaoyao Ye; Xiaowen Wu;

A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip

2011 / IEEE / 978-1-4577-0803-9
By: Jinwen Li; Minxuan Zhang; Chaochao Feng; Jantsch, A.; Zhonghai Lu; Jiang Jiang;

Physical Implementation of an Asynchronous 3D-NoC Router Using Serial Vertical Links

2011 / IEEE / 978-1-4577-0803-9
By: Vivet, P.; Sheibanyrad, A.; Darve, F.; Petrot, F.;

A DRAM Centric NoC Architecture and Topology Design Approach

2011 / IEEE / 978-1-4577-0803-9
By: Benini, L.; Murali, S.; Seiculescu, C.; De Micheli, G.;

A Simulation Based Buffer Sizing Algorithm for Network on Chips

2011 / IEEE / 978-1-4577-0803-9
By: Benini, L.; Kamakoti, V.; Murali, S.; Kumar, M.P.; Kumar, A.S.; De Micheli, G.;

Application Mapping onto Mesh Structured Network-on-Chip Using Particle Swarm Optimization

2011 / IEEE / 978-1-4577-0803-9
By: Sahu, P.K.; Chattopadhyay, S.; Gollapalli, S.; Venkatesh, P.;

Preprocessing-Based Run-Time Mapping of Applications on NoC-based MPSoCs

2011 / IEEE / 978-1-4577-0803-9
By: Singh, A.K.; Kaushik, S.; Srikanthan, T.;

Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis

2011 / IEEE / 978-1-4577-0803-9
By: Soumya, J.; Chattopadhyay, S.; Venkatesh, P.;

Intelligent On/Off Link Management for On-chip Networks

2011 / IEEE / 978-1-4577-0803-9
By: Theocharides, T.; Savva, A.G.; Soteriou, V.;

Application of Formal Methods for System-Level Verification of Network on Chip

2011 / IEEE / 978-1-4577-0803-9
By: Sowmya, A.; Palaniveloo, V.A.;

A Method for Integrating Network-on-Chip Topologies with 3D ICs

2011 / IEEE / 978-1-4577-0803-9
By: Murali, S.; Kumar, A.S.; Kumar, M.P.; Veezhinathan, K.; Benini, L.;

A flexible configuration approach for fault-tolerant multicast/unicast

2011 / IEEE / 978-1-61284-486-2
By: Hengzhu Liu; Jantsch, A.; Zhonghai Lu; Wenmin Hu; Dongpei Liu; Shixian Wang;

Design of a Crosspoint Queued router for a micro-network in SoCs

2011 / IEEE / 978-1-4244-8810-0
By: Wen-Fong Wang; Ching-Sung Lu; Jhih-Sian Li;

Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip

2011 / IEEE / 978-1-4577-0803-9
By: Xiaowen Wu; Jiang Xu; Yaoyao Ye; Weichen Liu; Wei Zhang; Zhehui Wang; Nikdast, M.; Xuan Wang;

A fault tolerant adaptive routing algorithm in 2D mesh network on chip

2011 / IEEE / 978-1-61284-486-2
By: Xiao CanWen; Zhang MinXuan; Wang YongQing;

A novel low-swing transceiver for interconnection between NoC routers

2011 / IEEE / 978-89-88678-47-3
By: Yi Liu; Zijin Li; Yintang Yang; Gang Liu;

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Topic: Network-on-chip

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