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Topic: Network Routing

Results

Tunable Inter-Resonator Coupling Structure With Positive and Negative Values and Its Application to the Field-Programmable Filter Array (FPFA)
2011 / IEEE
By: Juseop Lee; Chappell, W.J.; Peroulis, D.; Sigmarsson, H.H.; Naglich, E.J.;
Energy Efficiency QoS Assurance Routing in Wireless Multimedia Sensor Networks
2011 / IEEE
By: Rodrigues, J.J.P.C.; Kai Lin; Xuedong Liang; Naixue Xiong; Hongwei Ge;
Reach Adapting Algorithms for Mixed Line Rate WDM Transport Networks
2011 / IEEE
By: Manousakis, K.; Christodoulopoulos, K.; Varvarigos, E.;
An Algorithmic Study of Exact Route Matching for Integrated Circuits
2011 / IEEE
By: Hentschke, R.F.; Ozdal, M.M.;
Regenerator Placement Strategies for Translucent OBS Networks
2011 / IEEE
By: Pedrola, O.; Sole-Pareta, J.; Klinkowski, M.; Careglio, D.;
Co-Optimization and Analysis of Signal, Power, and Thermal Interconnects in 3-D ICs
2011 / IEEE
By: Young-Joon Lee; Sung Kyu Lim;
Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs
2011 / IEEE
By: Goel, S.K.; Chakrabarty, K.; Noia, B.; Verbree, J.; Marinissen, E.J.;
Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm
2011 / IEEE
By: Jain, T.N.K.; Gwan Choi; Sprintson, A.; Gratz, P.V.; Ramakrishna, M.;
Dynamic Programming Networks for Large-Scale 3D Chip Integration
2011 / IEEE
By: Chi-Sang Poon; Yakovlev, A.; Yicong Meng; Kai-Pui Lam; Kuan Zhou; Al-Dujaily, R.; Mak, T.;
An Analytical Model of the Propagation Induced Pulse Broadening (PIPB) Effects on Single Event Transient in Flash-Based FPGAs
2011 / IEEE
By: Sterpone, L.; Chipana, R.; Kastensmidt, F.L.; Battezzati, N.;
Survivable key management on WANETs
2011 / IEEE
By: Albini, L.C.P.; Santos, A.; Silva, E.; Nogueira, M.;
Introducing multi-ID and multi-locator into network architecture
2012 / IEEE
By: Kafle, V.P.; Inoue, M.;
A survey of information-centric networking
2012 / IEEE
By: Dannewitz, C.; Ahlgren, B.; Ohlman, B.; Kutscher, D.; Imbrenda, C.;
An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs
2012 / IEEE
By: Yao-Wen Chang; Po-Wei Lee; Chung-Wei Lin; Wei-Chih Tseng; Chin-Fang Shen;
A Dynamically Adjusting Gracefully Degrading Link-Level Fault-Tolerant Mechanism for NoCs
2012 / IEEE
By: Vitkovskiy, A.; Nicopoulos, C.; Soteriou, V.;
Subtractive Router for Tree-Driven-Grid Clocks
2012 / IEEE
By: Gunion, C.L.; Kozhaya, J.N.; Restle, P.J.; Haifeng Qian;
Cross-Contamination Avoidance for Droplet Routing in Digital Microfluidic Biochips
2012 / IEEE
By: Chakrabarty, K.; Yang Zhao;
HORNET: A Cycle-Level Multicore Simulator
2012 / IEEE
By: Keun Sup Shim; Myong Hyon Cho; Lis, M.; Pengju Ren; Fletcher, C.W.; Devadas, S.; Nanning Zheng; Khan, O.;
Obstacle-Avoiding Rectilinear Steiner Tree Construction: A Steiner-Point-Based Algorithm
2012 / IEEE
By: Sy-Yen Kuo; Chih-Hung Liu; Shih-Yi Yuan; Jung-Hung Weng; Chun-Syun Lin; Lee, D.T.;
Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010
2012 / IEEE
By: Anderson, J.H.; Gort, M.;
Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits
2012 / IEEE
By: Xin Zhao; Sung Kyu Lim; Mukhopadhyay, S.; Tolbert, J.R.;
Memory-Efficient On-Chip Network With Adaptive Interfaces
2012 / IEEE
By: Tenhunen, H.; Plosila, J.; Liljeberg, P.; Ebrahimi, M.; Daneshtalab, M.;
NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing
2012 / IEEE
By: Wong, M.D.F.; Qiang Ma;
Obstacle-Aware Clock-Tree Shaping During Placement
2012 / IEEE
By: Markov, I.L.; Dong-Jin Lee;
Postgrid Clock Routing for High Performance Microprocessor Designs
2012 / IEEE
By: Young, E.F.Y.; Wai-Chung Tang; Haitong Tian; Sze, C.N.;
Correctly Modeling the Diagonal Capacity in Escape Routing
2012 / IEEE
By: Tan Yan; Wong, M.D.F.;
A Reliable Routing Architecture and Algorithm for NoCs
2012 / IEEE
By: DeOrio, A.; Chen, G.; Jin Hu; Blaauw, D.; Sylvester, D.; Bertacco, V.; Fick, D.;
An Oblivious Routing Algorithm for 3D Mesh Networks to Achieve a New Worst-Case Throughput Bound
2012 / IEEE
By: Chia-Wei Chang; Guang Sun; Lieguang Zeng; Bill Lin;
Light-Weight On-Chip Monitoring Network for Dynamic Adaptation and Calibration
2012 / IEEE
By: Ituero, P.; Osuna, C.G.; Marcos, M.A.S.; Lopez-Vallejo, M.;
Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip
2012 / IEEE
By: Al-Dujaily, R.; Palesi, M.; Yakovlev, A.; Fei Xia; Mak, T.;
Using Transmission Lines for Global On-Chip Communication
2012 / IEEE
By: Hui Wu; Huang, M.; Jie Xu; Jianyun Hu; Carpenter, A.; Peng Liu;
Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges
2012 / IEEE
By: Ganguly, A.; Deb, S.; Deukhyoun Heo; Belzer, B.; Pande, P.P.;
Approximation Algorithms for Many-to-Many Traffic Grooming in Optical WDM Networks
2012 / IEEE
By: Kamal, A.E.; Saleh, M.A.;
Randomized Partially-Minimal Routing: Near-Optimal Oblivious Routing for 3-D Mesh Networks
2012 / IEEE
By: Ramanujam, R.S.; Bill Lin;
Multi-path routing in time-division-multiplexed networks on chip
2009 / IEEE / 978-1-4577-0236-5
By: Stefan, R.; Goossens, K.;
Highly efficient reconfigurable routers in Networks-on-Chip
2009 / IEEE / 978-1-4577-0236-5
By: Carro, L.; Concatto, C.; Matos, D.; Susin, A.; Kreutz, M.; Kastensmidt, F.;
A study on WK-recursive topology using gpNoCsim++ simulator and comparison to Other topologies
2009 / IEEE / 978-1-4577-0236-5
By: Ahrabi, A.A.A.; Bahrbegi, H.; Jamali, M.A.J.; Bahrbegi, M.;
Analysis of SET propagation in flash-based FPGAs by means of electrical pulse injection
2009 / IEEE / 978-1-4577-0493-2
By: Ferlet-Cavrois, V.; Sterpone, L.; Battezzati, N.;
Application research on network coding in WSN
2010 / IEEE / 978-1-4244-9954-0
By: Xu Fan; Chunguang Ma; Guoyin Zhang; Lei Wang;
Planar adaptive fault-tolerant routing in PRDT(2,1)-based NoCs
2010 / IEEE / 978-1-4244-8598-7
By: Zhen Zhang; Xinming Duan;
Gridless pin access in detailed routing
2011 / IEEE / 978-1-4503-0636-2
By: Nieberg, T.;
An optimal algorithm for layer assignment of bus escape routing on PCBs
2011 / IEEE / 978-1-4503-0636-2
By: Young, E.F.Y.; Qiang Ma; Wong, M.D.F.;
Optimization of routing and gateway allocation in aeronautical ad hoc networks using genetic algorithms
2011 / IEEE / 978-1-4244-9538-2
By: Hoffmann, F.; Wolisz, A.; Medina, D.;
SWIFT: A 2.1Tb/s 32�2 self-arbitrating manycore interconnect fabric
2011 / IEEE / 978-1-61284-175-5
By: Blaauw, D.; Mudge, T.; Sylvester, D.; Tai-Chuan Ou; Dreslinski, R.; Satpathy, S.;
Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries
2011 / IEEE / 978-1-4503-0636-2
By: Burns, S.; Ryzhenko, N.;
Mapping methodology and analysis of matrix-based nanocomputer architectures
2011 / IEEE / 978-1-61284-137-3
By: Jabeur, K.; Yakymets, N.; Le Beux, S.; O'Connor, I.;
Loopback output router for reliable Network on Chip
2011 / IEEE / 978-1-4577-1056-8
By: Killian, C.; Dandache, A.; Monteiro, F.; Tanougast, C.;
MO-Pack: Many-objective clustering for FPGA CAD
2011 / IEEE / 978-1-4503-0636-2
By: Rajavel, S.T.; Akoglu, A.;
A deadlock-free fault-tolerant routing algorithm based on pseudo-receiving mechanism for Networks-on-Chip of CMP
2011 / IEEE / 978-1-61284-774-0
By: Jinwen Li; Lunguo Xie; Yancang Chen; Zhonghai Lu;
Fault-tolerant 3D clock network
2011 / IEEE / 978-1-4503-0636-2
By: Shih-Hsiu Huang; Yu-Shih Su; Chiao-Ling Lung; Shih-Chieh Chang; Yiyu Shi;
Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA
2011 / IEEE / 978-1-4577-0642-4
By: Mehrez, H.; Marrakchi, Z.; Amouri, E.;
Efficient congestion-aware selection method for on-chip networks
2011 / IEEE / 978-1-4577-0642-4
By: Plosila, J.; Liljeberg, P.; Daneshtalab, M.; Ebrahimi, M.; Tenhunen, H.;
A Group-Preferential Parallel-Routing Algorithm for Cross-Referencing Digital Microfluidic Biochips
2011 / IEEE / 978-1-4577-0803-9
By: Dasgupta, P.; Rahaman, H.; Mandal, R.; Roy, P.;
A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip
2011 / IEEE / 978-1-4577-0803-9
By: Jinwen Li; Minxuan Zhang; Chaochao Feng; Jantsch, A.; Zhonghai Lu; Jiang Jiang;
Physical Implementation of an Asynchronous 3D-NoC Router Using Serial Vertical Links
2011 / IEEE / 978-1-4577-0803-9
By: Vivet, P.; Sheibanyrad, A.; Darve, F.; Petrot, F.;
Enhanced Redundant via Insertion with Multi-via Mechanisms
2011 / IEEE / 978-1-4577-0803-9
By: Ting-Feng Chang; Shanq-Jang Ruan; Shih-Hsien Yang; Tsang-Chi Kan;
A Hybrid RF/Metal Clock Routing Algorithm to Improve Clock Delay and Routing Congestion
2011 / IEEE / 978-1-4577-0803-9
By: Mohammadi-Arfa, Z.; Jahanian, A.;
Grey relational grade applied to FPGA placement with minimal wire length
2011 / IEEE / 978-1-61284-486-2
By: Jan-Ou Wu; Yang-Hsin Fan; Chien Wei; San-Fu Wang;
Location-Based IP Addressing in IP-Enable Wireless Sensor Networks
2011 / IEEE / 978-1-4577-0860-2
By: Rong Ding; Haiying Du;
Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs
2011 / IEEE / 978-1-4577-0803-9
By: Buttrick, M.; Kundu, S.;
A fault tolerant adaptive routing algorithm in 2D mesh network on chip
2011 / IEEE / 978-1-61284-486-2
By: Xiao CanWen; Zhang MinXuan; Wang YongQing;
Tuple Spaces in Hardware for Accelerated Implicit Routing
2011 / IEEE / 978-1-61284-425-1
By: Tripp, J.L.; Baker, Z.K.;
Online Routing of FPGA Clock Networks for Module Relocation in Partial Reconfigurable Multi Clock Designs
2011 / IEEE / 978-1-61284-425-1
By: Hubner, M.; Haetzer, B.; Schuck, C.; Becker, J.;
Improving Performance of Deterministic Single-Path Routing on 2-Level Generalized Fat-Trees
2011 / IEEE / 978-1-61284-425-1
By: Mahapatra, S.; Nienaber, W.; Xin Yuan;
A Unified Algorithm for Both Randomized Deterministic and Adaptive Routing in Torus Networks
2011 / IEEE / 978-1-61284-425-1
By: Underwood, K.D.; Borch, E.;
Power-Efficient Inter-Layer Communication Architectures for 3D NoC
2011 / IEEE / 978-1-4577-0803-9
By: Tenhunen, H.; Plosila, J.; Liljeberg, P.; Vaddina, K.R.; Latif, K.; Rahmani, A.-M.;
Circuit routing over heterogeneous optical networks
2011 / IEEE / 978-986-02-8974-9
By: Doverspike, R.; Chiu, A.; Dahai Xu; Dongmei Wang; Guangzhi Li;
A study on cell-level routing for VeSFET circuits
2011 / IEEE / 978-83-932075-2-7
By: Marek-Sadowska, M.; Xiang Qiu;
Implementation of signal processing tasks on neuromorphic hardware
2011 / IEEE / 978-1-4244-9637-2
By: Heliot, R.; Temam, O.;
GPU-Accelerated Wire-Length Estimation for FPGA Placement
2011 / IEEE / 978-1-4577-0635-6
By: Grewal, G.; Fobel, C.; Stacey, D.;
Obstacle-avoiding rectilinear Steiner minimum tree construction based on Discrete Particle Swarm Optimization
2011 / IEEE / 978-1-4244-9953-3
By: Yulong Shen; Wenzhong Guo; Qingzhen Liu;
Routing architecture and algorithms for a superconductivity circuits-based computing hardware
2011 / IEEE / 978-1-4244-9789-8
By: Mehdipour, F.; Murakami, K.; Inoue, K.; Kataoka, H.; Honda, H.;
Flexible simulation and modeling for 2D topology NoC system design
2011 / IEEE / 978-1-4244-9789-8
By: Khan, G.N.; Gharan, M.O.;
A novel placement algorithm for multi-pin digital microfluidic biochips
2011 / IEEE / 978-1-61284-857-0
By: Dasgupta, P.; Rahaman, H.; Roy, S.; Roy, P.;
DPSO-based Rectilinear Steiner Minimal Tree construction considering bend reduction
2011 / IEEE / 978-1-4244-9953-3
By: Wenzhong Guo; Guolong Chen; Genggeng Liu; Zhen Chen;
Link-sharing method of buffer in direct-connection network
2011 / IEEE / 978-1-4577-0253-2
By: Fukase, N.; Watanabe, S.; Miura, Y.;
A template router
2011 / IEEE / 978-1-4577-0618-9
By: Fernandez, F.V.; Dundar, G.; Unutulmaz, A.;
Longest Prefix Match and updates in Range Tries
2011 / IEEE / 978-1-4577-1292-0
By: Sourdis, I.; Katamaneni, S.H.;
Routing-aware placement algorithms for modern analog integrated circuits
2011 / IEEE / 978-1-61284-857-0
By: Chun-Po Huang; Cheng-Chung Lu; Cheng-Wu Lin; Jai-Ming Lin; Soon-Jyh Chang;
An information retrieval scheme for Delay and Tolerance Networks
2011 / IEEE / 978-1-4577-0321-8
By: Zhu Dongfeng; Cao Yuanda; Zhou Ruitao;
An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture
2011 / IEEE / 978-1-4503-0713-0
By: Ferreira, R.; Carro, L.; Pereira, M.M.; Mucida, L.; Vendramini, J.G.;
Wormhole Attacks Mitigation in Ad Hoc Networks
2011 / IEEE / 978-1-4577-0979-1
By: Azer, M.A.;
Towards On-the-Fly Incremental Updates for Virtualized Routers on FPGA
2011 / IEEE / 978-1-4577-1484-9
By: Hoang Le; Ganegedara, T.; Prasanna, V.K.;
FPGA Interconnect Architecture Exploration Based on a Statistical Model
2011 / IEEE / 978-1-4577-1484-9
By: Jinmei Lai; Ding Xie; Zhen Wang;
A Routing Architecture for Mapping Dataflow Graphs at Run-Time
2011 / IEEE / 978-1-4577-1484-9
By: Torresen, J.; Koch, D.;
IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs
2011 / IEEE / 978-1-4577-1484-9
By: Yu Hu; GengSheng Chen; Naifeng Jing; Zhe Feng; Lei He;
Timing-Driven Routing of High Fanout Nets
2011 / IEEE / 978-1-4577-1484-9
By: Xun Chen; Minxuan Zhang; Jianwen Zhu;
Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign
2011 / IEEE / 978-1-4577-1484-9
By: Wai-Kei Mak; Seong-I Lei;
Reconfigurable electro-optical logic in silicon photonic integrated circuits
2011 / IEEE / 978-1-4244-8340-2
By: Soref, R.; Qianfan Xu;
A new intrusion detection method based on FSM and cache memory in ad hoc networks
2011 / IEEE / 978-1-61284-204-2
By: Shahrbanoonezhad, A.; Jalali, D.S.;
A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers
2011 / IEEE / 978-1-4577-1048-3
By: Yoshimoto, M.; Kawaguchi, H.; Takeuchi, Y.; Nakata, Y.;
Towards an Efficient NoC Topology through Multiple Injection Ports
2011 / IEEE / 978-1-4577-1048-3
By: Eberle, H.; Duato, J.; Flich, J.; Camacho, J.; Olesinski, W.;
An Abstraction to Support Design of Deadlock-free Routing Algorithms for Large and Hierarchical NoCs
2011 / IEEE / 978-1-4577-0383-6
By: Kumar, S.; Holsmark, R.;
Policy-Driven Reconfiguration Incorporating Multi-objective Optimization for Performance Management in a Ship Backbone Network
2011 / IEEE / 978-1-4577-0383-6
By: Sungwoo Tak; Hyejin Kim;
Enhancing Performance of NoC-Based Architectures Using Heuristic Virtual-Channel Sharing Approach
2011 / IEEE / 978-0-7695-4439-7
By: Seceleanu, T.; Vaddina, K.R.; Rahmani, A.; Latif, K.; Tenhunen, H.; Liljeberg, P.;
Introduction of centralized and distributed routing protocols
2011 / IEEE / 978-1-4577-0321-8
By: He Xin;
Protocol Selector Using Mobile Agents for Routing in MANETs
2011 / IEEE / 978-1-4244-6252-0
By: Anand, P.; Sarje, A.K.;
Performance analysis of cluster based 3D routing algorithms for NoC
2011 / IEEE / 978-1-4244-9477-4
By: Viswanathan, N.; Somasundaram, K.; Paramasivam, K.;
Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores
2011 / IEEE / 978-1-4577-1954-7
By: Lewis, D.L.; Lee, H.-H.S.; Sung Kyu Lim; Xin Zhao; Panth, S.;
Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System
2011 / IEEE / 978-1-4577-1484-9
By: Pellauer, M.; Kinsy, M.A.; Devadas, S.;

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