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Topic: Network On Chip

Results

Temporal isolation on multiprocessing architectures
2011 / IEEE / 978-1-4503-0636-2
By: Lee, E.; Dai Bui; Reineke, J.; Patel, H.; Liu, I.;
DRAIN: Distributed Recovery Architecture for Inaccessible Nodes in multi-core chips
2011 / IEEE / 978-1-4503-0636-2
By: DeOrio, A.; Li-Shiuan Peh; Bertacco, V.; Aisopos, K.;
Fault-tolerance assessment and enhancement in SoCWire interface: A system-on-chip wire
2011 / IEEE / 978-1-4577-1056-8
By: Salamat, R.; Zarandi, H.R.;
Loopback output router for reliable Network on Chip
2011 / IEEE / 978-1-4577-1056-8
By: Killian, C.; Dandache, A.; Monteiro, F.; Tanougast, C.;
Wormhole routing optimization algorithm based on virtual channel switching
2011 / IEEE / 978-1-61284-774-0
By: Xiangxiang Zhang; Mingxiang Zang; Wen Jia;
Simulations of NoC topologies for generalized hierarchical completely-connected networks
2011 / IEEE / 978-1-4577-0642-4
By: Takabatake, T.;
Application of Formal Methods for System-Level Verification of Network on Chip
2011 / IEEE / 978-1-4577-0803-9
By: Sowmya, A.; Palaniveloo, V.A.;
A fault tolerant adaptive routing algorithm in 2D mesh network on chip
2011 / IEEE / 978-1-61284-486-2
By: Xiao CanWen; Zhang MinXuan; Wang YongQing;
Flexible simulation and modeling for 2D topology NoC system design
2011 / IEEE / 978-1-4244-9789-8
By: Khan, G.N.; Gharan, M.O.;
Link-sharing method of buffer in direct-connection network
2011 / IEEE / 978-1-4577-0253-2
By: Fukase, N.; Watanabe, S.; Miura, Y.;
FPGA implementation of network on chip based on Pentacle topology
2011 / IEEE / 978-1-4577-0321-8
By: Jian-Xian Zhang; Duan Zhou; Xiang Gao; Rui Lai; Yin-Tang Yang;
Cost of Sparse Mesh Layouts Supporting Throughput Computing
2011 / IEEE / 978-1-4577-1048-3
By: Forsell, M.; Penttonen, M.; Leppanen, V.;
Performance evaluation of scheduling algorithms in network on chip
2011 / IEEE / 978-1-4577-0894-7
By: Xiaojie Hao; Yonghui Li; Daibing Zeng; Baojian Shu; Huaxi Gu;
PEPCP: A Power-Efficient Parallel Coherence Protocol for Large-Scale Network-on-Chip
2011 / IEEE / 978-1-4577-1336-1
By: Wei Wang; Lin Qiao; Fucen Zeng;
A Distributed Switch Architecture for On-Chip Networks
2011 / IEEE / 978-1-4577-1336-1
By: Silla, F.; Flich, J.; Hernandez, C.; Roca, A.; Duato, J.;
A Fault Tolerant Hierarchical Network on Chip Router Architecture
2011 / IEEE / 978-1-4577-1713-0
By: Neishaburi, M.H.; Zilic, Z.;
Debug Aware AXI-based Network Interface
2011 / IEEE / 978-1-4577-1713-0
By: Neishaburi, M.H.; Zilic, Z.;
An Input Buffer Architecture for On-chip Routers
2011 / IEEE / 978-1-4577-1796-3
By: Oyanagi, S.; Chu Van Thiem;
Hardware implementation of link aggregation in networks-on-chip
2011 / IEEE / 978-1-4673-0126-8
By: Lysenko, O.; Korotkyi, I.;
Highly reliable and power efficient NOC interconnects
2011 / IEEE / 978-1-4577-0516-8
By: Ismail, M.; Hofmann, K.; Abd El Ghany, M.A.; Zamzam, D.M.;
An Authenticated Encryption Based Security Framework for NoC Architectures
2011 / IEEE / 978-1-4577-1880-9
By: Kapoor, H.K.; Sajeesh, K.;
Encoding Technique for Reducing Power Dissipation in Network on Chip Serial Links
2011 / IEEE / 978-0-7695-4587-5
By: Sarma, D.N.; Lakshminarayanan, G.;
A test method of interconnection online detection of NoC based on 2D Torus topology
2011 / IEEE / 978-1-4244-7853-8
By: Gang Luo; Yong Le Xie; Shuo Li; Hao Liang; Shu Yan Jiang;
Evaluating the Problem of Process Mapping on Network-on-Chip for Parallel Applications
2011 / IEEE / 978-0-7695-4613-1
By: Navaux, P.O.A.; Freitas, H.C.; Oliveira, P.A.C.; Avelar, C.P.;
A Multiphase Routing Scheme in Irregular Mesh-Based NoCs
2011 / IEEE / 978-1-4577-1808-3
By: Xinming Duan; Yuanyuan Li;
Design and performance evaluation of on chip network with Transaction Level Modeling
2011 / IEEE / 978-1-4577-2209-7
By: Tourki, R.; Zitouni, A.; Attia, B.; Chouchene, W.; Abid, N.;
A Quality of Service Network on Chip based on a new priority arbitration mechanism
2011 / IEEE / 978-1-4577-2209-7
By: Noureddine, A.; Attia, B.; Wissem, C.; Tourki, R.; Zitouni, A.;
Migrating single FPGA chip multiprocessor with network on chip to 65nm and 45nm ASIC
2011 / IEEE / 978-1-4577-2209-7
By: Wang, Z.; Hammami, O.; Houzet, D.;
NoC architecture with local bus design for network coding
2011 / IEEE / 978-1-4577-0101-6
By: Zhang Si-wei; Hu Jian-hao;
Loopback Virtual Channel Router Architecture for Network on Chip
2012 / IEEE / 978-1-4673-0798-7
By: Suseela, J.; Muthukumar, V.;
A Mixed Verification Strategy Tailored for Networks on Chip
2012 / IEEE / 978-1-4673-0973-8
By: Tsiligiannis, G.; Pierre, L.;
Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects
2012 / IEEE / 978-0-7695-4688-9
By: Pontes, J.; Vivet, P.; Calazans, N.;
Exploiting Dynamic Voltage and Frequency Scaling in networks on chip
2012 / IEEE / 978-1-4577-0833-6
By: Nanfang Li; Giaccone, P.; Bianco, A.;
Application-specific network-on-chip with link aggregation
2012 / IEEE / 978-9940-9436-0-8
By: Lysenko, Oleksandr; Korotkyi, Ievgen;
A new hybrid topology for network on chip
2012 / IEEE / 978-1-4673-1148-9
By: Mousavi, Mahsa; Tahghighi, Mohammad; Bazargan, Kia; Khadivi, Pejman;
A real-time silicon cerebellum spiking neural model based on FPGA
2014 / IEEE
By: Luo, Junwen; Tin, Chung; Mak, Terrence; Yamazaki, Tadashi; Degenaar, Patrick; Coapes, Graeme;
DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs
2015 / IEEE
By: Tenhunen, Hannu; Hemani, Ahmed; Ellerve, Peeter; Jafri, S.M.A.; Tajammul, Muhammad Adeel; Plosila, Juha;
High-efficient queue-based spin locks for Network-on-Chip processors
2014 / IEEE
By: Liu, Peilin; Wei, Zhenqi; Ying, Rendong; Sun, Rongdi;
Problems encountered in various arbitration techniques used in NOC router: A survey
2015 / IEEE
By: Mondai, Abir J; Majumder, Alak; Singh, Sandeep K; Jain, Kunj;
A Wormhole NoC Protocol for Mixed Criticality Systems
2014 / IEEE
By: Burns, A.; Indrusiak, L.S.; Harbin, J.;
On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs
2015 / IEEE
By: Cilardo, Alessandro; Flich, Jose; Fusella, Edoardo; Mazzeo, Antonino;
An FPGA-based multi-core system for synthetic aperture radar data processing
2014 / IEEE
By: Song, Yukun; Du, Gaoming; Zhang, Duoli; Hou, Ning;
High performance computing for sound wave using multi channel digital I/Q demodulator
2013 / IEEE
By: Shibu R M; Gopalakrishnan, Arun;
Performance evalulation of different routing algorithms in Network on Chip
2013 / IEEE
By: Mahapatra, Kamala Kanta; Kamal Reddy, Tetala Neel; Swain, Ayas Kanta; Singh, Jayant Kumar;
An efficient routing scheme for irregular mesh NoCs
2013 / IEEE
By: Qingli Xiao; Dexue Zhang; Lu Zheng; Hongzhou Fu;
Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link
2014 / IEEE
By: Shirahama, Hirokatsu; Mochizuki, Akira; Hanyu, Takahiro;
Crosstalk-Aware Multiple Error Detection Scheme Based on Two-Dimensional Parities for Energy Efficient Network on Chip
2014 / IEEE
By: Hashim, S. J.; Samsudin, K.; Flayyih, W. N.; Ismail, Y. I.; Rokhani, F. Z.;
CAP: Communication aware programming
2014 / IEEE
By: Heisswolf, Jan; Zaib, Aurang; Becker, Jurgen; Herkersdorf, Andreas; Snelting, Gregor; Henkel, Jorg; Teich, Jurgen; Weichslgartner, Andreas; Zwinkau, Andreas; Kobbe, Sebastian;
An area-efficient hexagonal interconnection network for multi-core processors
2014 / IEEE
By: Wang, Xiaofang; Kresch, Edward;
Network-on-Chip Implementation of Midimew-Connected Mesh Network
2013 / IEEE
By: Awal, Md Rabiul; Rahman, M.M. Hafizur;
Design and Implementation of Various Topologies for Networks on Chip and Its Performance Evolution
2014 / IEEE
By: Gugulothu, Somulu; Chawhan, M.D.;
Evaluation of highly conditionally diagnosable (n, k)-star topology for applications in resilient Network on Chip
2014 / IEEE
By: Bai, Li; Korostelev, Michael; Gong, Ning; Ferrese, Frank; Biswas, Saroj K.;
QaMC - QoS Aware Multicast router for NoC fabric
2014 / IEEE
By: Nambiar, Sandeep Gopi; Ko, Seok-Bum; Lakshminarayanan, G.; Swaminathan, K.;
A novel hybrid topology for Network on Chip
2014 / IEEE
By: Ko, Seok-Bum; Lakshminarayanan, G.; Rajkumar; Gopi, Sandeep; Swaminathan, K.;
Top Picks from the 2013 Computer Architecture Conferences
2014 / IEEE
By: Thottethodi, Mithuna S.; Mukherjee, Shubu;
Smart: Single-Cycle Multihop Traversals over a Shared Network on Chip
2014 / IEEE
By: Krishna, Tushar; Peh, Li-Shiuan; Kwon, Woo-Cheol; Chen, Chia-Hsin Owen;
Low Energy Mapping Techniques under Reliability and Bandwidth Constraints
2013 / IEEE
By: Palesi, Maurizio; Masi, Marina; Mineo, Andrea; Catania, Vincenzo; Ascia, Giuseppe;
Design and evaluation of virtual channel router for mesh-of-grid based NoC
2014 / IEEE
By: Anjali, N. V.; Somasundaram, K.;
Central Switch Noded Mesh architecture (CSNM)
2014 / IEEE
By: Seok-Bum Ko; Lakshminarayanan, G.; Swaminathan, K.; Nambiar, Sandeep Gopi;
An Adaptive Routing of the 2-D Torus Network Based on Turn Model
2013 / IEEE
By: Matoyama, Kazuya; Watanabe, Shigeyoshi; Shimozono, Kentaro; Miura, Yasuyuki;
High throughput asynchronous NoC switch for high process variation
2013 / IEEE
By: Ezz-Eldin, Rabab; Hamed, Hesham F. A.; El-Moursy, Magdy A.;
Asynchronous high throughput NoC under high process variation
2013 / IEEE
By: Ezz-Eldin, Rabab; Hamed, Hesham F. A.; El-Moursy, Magdy A.;
Analysis of power consumption on switch fabrics in network routers
2002 / IEEE / 1-58113-461-4
By: Benini, L.; Ye, T.T.; De Micheli, G.;
Algorithms and tools for network on chip based system design
2003 / IEEE / 0-7695-2009-X
By: Tang Lei; Kumar, S.;
Load distribution with the proximity congestion awareness in a network on chip
2003 / IEEE / 0-7695-1870-2
By: Nilsson, E.; Jantsch, A.; Oberg, J.; Millberg, M.;
Evaluating application mapping using network simulation
2003 / IEEE / 0-7803-8160-2
By: Soininen, J.-P.; Salminen, T.;
A generic reconfigurable neural network architecture as a network on chip
2004 / IEEE / 0-7803-8445-8
By: Theocharides, T.; Srikantam, V.; Invin, M.J.; Vijaykrishnan, N.; Link, G.;
Communication on a segmented bus
2004 / IEEE / 0-7803-8445-8
By: Seceleanu, T.;
Architectural, system level and protocol level techniques for power optimization for networked embedded systems
2005 / IEEE / 0-7695-2264-5
By: Benini, L.; Gupta, R.K.; Shuklam SK;
MultiNoC: a multiprocessing system enabled by a network on chip
2005 / IEEE / 0-7695-2288-2
By: Moller, L.; Mello, A.; Moraes, F.; Calazans, N.;
Arbitration for the segmented bus architecture
2004 / IEEE / 0-7803-8499-7
By: Stancescu, S.; Seceleanu, T.;
Mapping concurrent applications to a NoC
2004 / IEEE / 0-7803-8511-X
By: Tang Lei; Yang Yanhui; Peng Hong;
VLSI architecture based on packet data transfer scheme and its application
2005 / IEEE / 0-7803-8834-8
By: Kameyama, M.; Homma, Y.; Tomabechi, N.; Fujioka, Y.;
Slack-time aware routing in NoC systems
2005 / IEEE / 0-7803-8834-8
By: Andreasson, D.; Kumar, S.;
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip
2005 / IEEE / 0-7803-8736-8
By: Chih-Chieh Chou; Pao-Jui Huang; Cheng-Yeh Wang; Liang-Yu Lin; Jing-Yang Jou;
Asynchronous network node design for network-on-chip
2005 / IEEE / 0-7803-9029-6
By: Xin Wang; Nurmi, J.; Ahonen, T.; Siguenza-Tortosa, D.;
Starvation-free arbitration policies for the segmented-bus platform
2005 / IEEE / 0-7803-9029-6
By: Seceleanu, T.; Nevalainen, O.; Knuutila, T.;
Analysis of error recovery schemes for networks on chips
2005 / IEEE
By: De Micheli, G.; Benini, L.; Irwin, M.J.; Vijaykrishnan, N.; Theocharides, T.; Murali, S.;
Dynamic interconnection of reconfigurable modules on reconfigurable devices
2005 / IEEE
By: Bobda, C.; Ahmadinia, A.;
Extended-butterfly fat tree interconnection (EFTI) architecture for network on chip
2005 / IEEE / 0-7803-9195-0
By: Hossain, H.; Islam, M.; Akbar, M.;
Replacing global wires with an on-chip network: a power analysis
2005 / IEEE / 1-59593-137-6
By: Heo, S.; Asanovic, K.;
A low-power crossroad switch architecture and its core placement for network-on-chip
2005 / IEEE / 1-59593-137-6
By: Tien-Fu Chen; Jih-Sheng Shen; Kuei-Chung Chang;
Design, mapping, and simulations of a 3G WCDMA/FDD base station using network on chip
2005 / IEEE / 0-7695-2403-6
By: Liu, D.; Wiklund, D.;
A High-Performance Router Design for VDSM NoCs
2005 / IEEE / 0-7803-9264-7
By: Sridhar, R.; Srinivasan, K.; Narasimhan, A.;
Network on chip using a reconfigurable platform
2003 / IEEE / 0-7803-8294-3
By: Li Ping Sun; David, J.-P.; El Mostapha Aboulhamid;
Evaluation of pseudo adaptive XY routing using an object oriented model for NOC
2005 / IEEE / 0-7803-9262-0
By: Afzali-kusha, A.; Nickray, M.; Dehyadgari, M.; Navabi, Z.;
Mapping applications to NoC platforms with multithreaded processor resources
2005 / IEEE / 1-4244-0064-3
By: Kumar, S.; Pop, R.;
Improving BE traffic QoS using GT slack in NoC systems
2005 / IEEE / 1-4244-0064-3
By: Andreasson, D.; Kumar, S.;
A dynamic routing mechanism for network on chip
2005 / IEEE / 1-4244-0064-3
By: Hellebrand, S.; Welzl, M.; Ali, M.;
SystemC implementation of a NoC
2005 / IEEE / 0-7803-9484-4
By: Portero, A.; Carrabina, J.; Pla, R.;
Towards Massively Parallel Numerical Computations Based on Dynamic SMP Clusters with Communication on the Fly
2005 / IEEE / 0-7695-2434-6
By: Masko, L.; Tudruj, M.;
On-line fault detection and location for NoC interconnects
2006 / IEEE / 0-7695-2620-9
By: Saleh, R.; Ivanov, A.; Grecu, C.; Partha Pratim Pande; Sogomonyan, E.S.;
Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems
2006 / IEEE / 1-59593-381-6
By: Chi-Ying Tsui; Lap-Fai Leung;
DyXY - a proximity congestion-aware deadlock-free dynamic routing method for network on chip
2006 / IEEE / 1-59593-381-6
By: Qing-An Zeng; Ming Li; Wen-Ben Jone;
On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures
2006 / IEEE / 0-7695-2609-8
By: Greiner, A.; Petrot, F.; Gomez, P.;
A complete 4G radiocommunication application mapping onto a 2D mesh NoC architecture
2006 / IEEE / 1-4244-0416-9
By: Houzet, D.; Delorme, J.;
Simple Design Criterion for Maximizing Data Rate in NoC Links
2006 / IEEE / 1-4244-0454-1
By: Goren, D.; Barger, A.; Kolodny, A.;
An optimum mapping of IPs for On-Chip Network design based on the minimum latency constraint
2005 / IEEE / 0-7803-9312-0
By: Vu-Duc Ngo; Hae-Wook Choi;
Simulation and Evaluation for SS Network on Chip architecture using OPNET
2006 / IEEE / 1-4244-0161-5
By: HongZhi Zhao; Qin Wang;
The Optimized Tree-based Network on Chip Topologies for H.264 Decoder Design
2006 / IEEE / 1-4244-0271-9
By: Hae-Wook Choi; Vu-Duc Ngo; Hanjin Cho; Younghwan Bae;

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