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Topic: Multiprocessor Interconnection Networks

Results

CNoC: High-Radix Clos Network-on-Chip
2011 / IEEE
By: Chao, H.J.; Artan, N.S.; Ming Yang; Yu-Hsiang Kao;
Strong Diagnosability and Conditional Diagnosability of Augmented Cubes Under the Comparison Diagnosis Model
2012 / IEEE
By: Sun-Yuan Hsieh; Won-Sin Hong;
Tianhe-1A Interconnect and Message-Passing Services
2012 / IEEE
By: Min Xie; Xuejun Yang; Hongjia Cao; Lu Liu; Kefei Wang; Yutong Lu;
The IBM Blue Gene/Q Interconnection Fabric
2012 / IEEE
By: Satterfield, D.; Salapura, V.; Kumar, S.; Senger, R.M.; Sugawara, Y.; Steinmacher-Burow, B.; Heidelberger, P.; Eisley, N.A.; Dong Chen; Parker, J.;
On the Impact of Within-Die Process Variation in GALS-Based NoC Performance
2012 / IEEE
By: Silla, F.; Roca, A.; Hernandez, C.; Duato, J.; Flich, J.;
AWGR-based optical topologies for scalable and efficient global communications in large-scale multi-processor systems
2012 / IEEE
By: Xiaohui Ye; Akella, V.; Yoo, S.J.B.;
Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip
2012 / IEEE
By: Al-Dujaily, R.; Palesi, M.; Yakovlev, A.; Fei Xia; Mak, T.;
Using Transmission Lines for Global On-Chip Communication
2012 / IEEE
By: Hui Wu; Huang, M.; Jie Xu; Jianyun Hu; Carpenter, A.; Peng Liu;
Exploiting New Interconnect Technologies in On-Chip Communication
2012 / IEEE
By: Loh, G.; Kiyoung Choi; Kim, J.;
A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions
2012 / IEEE
By: Sahuquillo, J.; Ubal, R.; Kaeli, D.; Lopez, P.; Petit, S.;
China's homegrown supercomputers
2012 / IEEE
By: Calamia, J.;
Photonic interconnection network architectures using wavelength-selective spatial routing for chip-scale communications
2012 / IEEE
By: Chan, J.; Bergman, K.;
Silicon-based devices for computer interconnects
2010 / IEEE / 978-1-4244-9854-3
By: Zhechao Wang; Wosinski, L.;
On the optimum switch radix in fat tree networks
2011 / IEEE / 978-1-4244-8456-0
By: Rodriguez, G.; Luijten, R.P.; Minkenberg, C.;
SWIFT: A 2.1Tb/s 32�2 self-arbitrating manycore interconnect fabric
2011 / IEEE / 978-1-61284-175-5
By: Blaauw, D.; Mudge, T.; Sylvester, D.; Tai-Chuan Ou; Dreslinski, R.; Satpathy, S.;
A stochastic network calculus based approach for on-chip networks
2011 / IEEE / 978-988-17255-9-2
By: Chen Jin-Wen; Zhu Jin; Xi Hong-Sheng; Tang Liang;
A design space exploration of transmission-line links for on-chip interconnect
2011 / IEEE / 978-1-61284-660-6
By: Jianyun Hu; Carpenter, A.; Peng Liu; Hui Wu; Huang, M.;
Wormhole routing optimization algorithm based on virtual channel switching
2011 / IEEE / 978-1-61284-774-0
By: Xiangxiang Zhang; Mingxiang Zang; Wen Jia;
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems
2011 / IEEE / 978-1-61284-660-6
By: Junyoung Park; Abraham, J.A.;
On Nonblocking Folded-Clos Networks in Computer Communication Environments
2011 / IEEE / 978-1-61284-372-8
By: Xin Yuan;
vFtree - A Fat-Tree Routing Algorithm Using Virtual Lanes to Alleviate Congestion
2011 / IEEE / 978-1-61284-372-8
By: Reinemo, S.; Bogdanski, B.; Wei Lin Guay; Skeie, T.; Lysne, O.;
A fault tolerant adaptive routing algorithm in 2D mesh network on chip
2011 / IEEE / 978-1-61284-486-2
By: Xiao CanWen; Zhang MinXuan; Wang YongQing;
Improving Performance of Deterministic Single-Path Routing on 2-Level Generalized Fat-Trees
2011 / IEEE / 978-1-61284-425-1
By: Mahapatra, S.; Nienaber, W.; Xin Yuan;
A Unified Algorithm for Both Randomized Deterministic and Adaptive Routing in Torus Networks
2011 / IEEE / 978-1-61284-425-1
By: Underwood, K.D.; Borch, E.;
A Performance Model of Direct Numerical Simulation for Analyzing Large-Scale Systems
2011 / IEEE / 978-1-61284-425-1
By: Barker, K.J.; Kerbyson, D.J.;
Critical Bubble Scheme: An Efficient Implementation of Globally Aware Network Flow Control
2011 / IEEE / 978-1-61284-372-8
By: Lizhong Chen; Pinkston, T.M.; Ruisheng Wang;
Link-sharing method of buffer in direct-connection network
2011 / IEEE / 978-1-4577-0253-2
By: Fukase, N.; Watanabe, S.; Miura, Y.;
QUonG: A GPU-based HPC System Dedicated to LQCD Computing
2011 / IEEE / 978-1-4577-0635-6
By: Lonardo, A.; Lo Cicero, F.; Frezza, O.; Biagioni, A.; Ammendola, R.; Paolucci, P.S.; Tosoratto, L.; Vicini, P.; Simula, F.; Rossetti, D.;
A Network Calculus Model for SpaceWire Networks
2011 / IEEE / 978-1-4577-1118-3
By: Frances, F.; Ferrandiz, T.; Fraboul, C.;
Programmable NoC scheduling based on multi-core processor
2011 / IEEE / 978-1-4244-8165-1
By: Li Xianjie; Zhou Kuanjiu; Wang Jie; Cui Kai; Shen Shen;
The impact of test instrumentation with distributed processing capabilities on test program set (TPS) architecture and development
2011 / IEEE / 978-1-4244-9363-0
By: McGoldrick, M.;
The Tofu Interconnect
2011 / IEEE / 978-1-4577-1563-1
By: Ajima, Y.; Shimizu, T.; Hiramoto, S.; Inoue, T.; Takagi, Y.;
Evaluation of an Alternative for Increasing Switch Radix
2011 / IEEE / 978-1-4577-1052-0
By: Duato, J.; Alfaro, F.J.; Sanchez, J.L.; Andujar, F.J.; Villar, J.A.;
Combining Congested-Flow Isolation and Injection Throttling in HPC Interconnection Networks
2011 / IEEE / 978-1-4577-1336-1
By: Duato, J.; Quiles, F.J.; Lysne, O.; Skeie, T.; Escudero-Sahuquillo, J.; Flich, J.; Garcia, P.J.; Gran, E.G.;
Evaluating the Potential of Cray Gemini Interconnect for PGAS Communication Runtime Systems
2011 / IEEE / 978-1-4577-1563-1
By: ten Bruggencate, M.; Vishnu, A.; Olson, R.;
Predictive and Distributed Routing Balancing for High Speed Interconnection Networks
2011 / IEEE / 978-1-4577-1355-2
By: Castillo, C.N.; Luque, E.; Franco, D.; Lugones, D.;
C-Switches: Increasing Switch Radix with Current Integration Scale
2011 / IEEE / 978-1-4577-1564-8
By: Duato, J.; Alfaro, F.J.; Sanchez, J.L.; Andujar, F.J.; Villar, J.A.;
Analyzing the Performance Bottlenecks of the POWER7-IH Network
2011 / IEEE / 978-1-4577-1355-2
By: Barker, K.J.; Kerbyson, D.J.;
A Distributed Switch Architecture for On-Chip Networks
2011 / IEEE / 978-1-4577-1336-1
By: Silla, F.; Flich, J.; Hernandez, C.; Roca, A.; Duato, J.;
Analysis of on-chip interconnection network interface reliability in multicore systems
2011 / IEEE / 978-1-4577-1954-7
By: Pasricha, S.; Yi Xiang; Yong Zou;
An effective buffer space management in Serial RapidIO endpoint
2011 / IEEE / 978-1-4577-1610-2
By: Wang Yuan; Jia Song; Wu Fengfeng;
On-chip structure and addressing scheme design for 2-D block data processing in a 64-core array system
2011 / IEEE / 978-1-4577-0170-2
By: Zhigang Mao; Huimin Xing; Jing Xie;
Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC)
2011 / IEEE / 978-1-4577-0170-2
By: Trajkovic, J.; Le Beux, S.; Nicolescu, G.; O'Connor, I.;
A low-swing crossbar and link generator for low-power networks-on-chip
2011 / IEEE / 978-1-4577-1400-9
By: Sunghyun Park; Chen, C.-H.O.; Li-Shiuan Peh; Krishna, T.;
ATree-based topology synthesis for on-chip network
2011 / IEEE / 978-1-4577-1400-9
By: Cong, J.; Bo Yuan; Yuhui Huang;
The IBM Blue Gene/Q interconnection network and message unit
2011 / IEEE / 978-1-4503-0771-0
By: Parker, J.J.; Steinmacher-Burow, B.; Satterfield, D.L.; Salapura, V.; Kumar, S.; Dong Chen; Senger, R.M.; Heidelberger, P.; Eisley, N.A.; Sugawara, Y.;
A deadlock-free fault-tolerant routing algorithm for N-dimesional meshes
2011 / IEEE / 978-1-4577-1997-4
By: Xinming Duan; Jigang Wu;
A Numerical Solution for Throughput Improvement of On-chip Irregular Mesh Interconnection Network
2011 / IEEE / 978-1-4673-0060-5
By: Rostampour, S.; Rezazadeh, A.; Momeni, L.;
An Efficient Streaming Star Network for Multi-core Parallel DSP Processor
2011 / IEEE / 978-1-4577-1796-3
By: Karlsson, A.; Sohl, J.; Jian Wang; Liu, D.;
Toward All Optical Interconnections in Chip Multiprocessor (2)
2011 / IEEE / 978-0-7695-4551-6
By: Channoufi, M.; Garcia, S.; Delacressonniere, B.; Attia, R.; Lecoy, P.;
The Conditional Connectivity of M�bius Cubes under the 1-Safe Condition
2011 / IEEE / 978-1-4577-1419-1
By: Zhang Zongyun; Liu Shizhong; Zhang Jing;
Implementation and analysis of speculative flow control for on-chip interconnection network
2011 / IEEE / 978-1-4673-0498-6
By: Hung-Jen Sun; Yarsun Hsu;
Evaluation of All Routes and Terminal Reliability in the Data Vortex All Optical Switch for High Performance Computing
2011 / IEEE / 978-0-7695-4587-5
By: Chadha, D.; Sharma, N.; Chandra, V.;
Analyzing software inter-task communication channels on a clustered shared memory multi processor system-on-chip
2011 / IEEE / 978-1-4577-0621-9
By: Pouillon, N.; Genius, D.;
A test method of interconnection online detection of NoC based on 2D Torus topology
2011 / IEEE / 978-1-4244-7853-8
By: Gang Luo; Yong Le Xie; Shuo Li; Hao Liang; Shu Yan Jiang;
On the influence of selection function on the performance of fat-trees under hot-spot traffic
2011 / IEEE / 978-1-4577-0476-5
By: El-Boghdadi, H.M.; Farouk, A.;
An Algorithm to Find Optimal Independent Spanning Trees on Twisted-Cubes
2011 / IEEE / 978-1-4577-1808-3
By: Yuejuan Han; Jianxi Fan; Yan Wang;
Run-Time Computation and Communication Aware Mapping Heuristic for NoC-Based Heterogeneous MPSoC Platforms
2011 / IEEE / 978-1-4577-1808-3
By: Wu Jigang; Singh, A.K.; Kaushik, S.; Srikanthan, T.;
Stochastic modeling of Scouting Switching for adaptively-routed mesh networks
2011 / IEEE / 978-1-4577-0476-5
By: Zebardast, M.; Safaei, F.;
Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture
2011 / IEEE / 978-1-4577-1740-6
By: Fujita, M.; Krishnamoorthy, R.; Nandy, S.K.; Varadarajan, K.;
Achieving High Throughput in High-Radix Switch
2011 / IEEE / 978-1-4577-2135-9
By: Kefei Wang; Songqiao Chen; Ming Fang;
MINoC: Providing configurable high throughput interconnection for MPSoCs
2012 / IEEE / 978-1-4673-1208-0
By: Matos, D.; Reinbrecht, C.; Kreutz, M.; Susin, A.; Carro, L.;
SpaceWire standard and improved wormhole router design
2012 / IEEE / 978-1-4577-0557-1
By: Lixin Yu; Dalu Yi; Xingyou Wang; Haidong Fei;
A Network-on-Chip simulation framework for homogeneous Multi-Processor System-on-Chip
2011 / IEEE / 978-1-61284-193-9
By: Chia Yee Ooi; Marsono, M.N.; Yuan Wen Hau; Khalil-Hani, M.;
P2i-torus: A hybrid artchitecutre for direct interconnection
2011 / IEEE / 978-1-4577-1587-7
By: Menghan Li; Chao Zhang;
Reconfigurable interconnect infrastructure for multi-FPGA-based adaptive multiprocessing systems
2011 / IEEE / 978-1-4577-0200-6
By: Philipp, F.; Samman, F.A.; Glesner, M.;
Optimal Configuration of High-Radix Combined Switches
2012 / IEEE / 978-1-4673-0226-5
By: Andujar, F.J.; Villar, J.A.; Duato, J.; Alfaro, F.J.; Sanchez, J.L.;
A New Fault Injection Approach for Testing Network-on-Chips
2012 / IEEE / 978-1-4673-0226-5
By: Reorda, M.S.; Sabena, D.; Sterpone, L.;
A multi-core high-order A-stable and L-stable integration method for fast transient simulation of high-speed interconnect and transmission line circuits
2012 / IEEE / 978-1-4673-1504-3
By: Nakhla, M.; Gad, E.; Farhan, M.; Achar, R.;
A low-overhead monitoring ring interconnect for MPSoC parameter optimization
2012 / IEEE / 978-1-4673-1188-5
By: Herkersdorf, A.; Stechele, W.; Zeppenfeld, J.; Lakhtel, A.; Bouajila, A.;
Evaluating Qlogic's Dispersive Routing on High Performance Clusters
2012 / IEEE / 978-1-4673-1366-7
By: Al-Shaikh, R.; Sait, S.M.;
Constructing transition matrices for routing BPC permutations on shuffle-exchange recirculating networks
2012 / IEEE / 978-1-4673-0734-5
By: Ackarachalanonth, S.; Veselovsky, G.;
TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers
2012 / IEEE / 978-1-4673-0973-8
By: Menezo, L.G.; Prieto, P.; Abad, P.; Gregorio, J.-A.; Puente, V.; Colaso, A.;
CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers
2012 / IEEE / 978-1-4673-0973-8
By: Seiculescu, C.; Volos, S.; De Micheli, G.; Falsafi, B.; Pour, N.K.; Grot, B.;
Invited talk: Nanophotonic interconnection networks for performance-energy optimized computing
2012 / IEEE / 978-1-4577-1738-3
By: Bergman, K.;
A novel low-waveguide-crossing floorplan for fat tree based optical networks-on-chip
2012 / IEEE / 978-1-4577-1619-5
By: Jiang Xu; Zhehui Wang; Zhe Wang; Xuan Wang; Xiaowen Wu; Nikdast, M.; Weichen Liu; Wei Zhang; Yaoyao Ye;
A case for random shortcut topologies for HPC interconnects
2012 / IEEE / 978-1-4673-0476-4
By: Matsutani, H.; Koibuchi, M.; Casanova, H.; Hsu, D.F.; Amano, H.;
Exploiting Dynamic Voltage and Frequency Scaling in networks on chip
2012 / IEEE / 978-1-4577-0833-6
By: Nanfang Li; Giaccone, P.; Bianco, A.;
Design of Networks-on-Chip for Real-Time Multi-processor Systems-on-Chip
2012 / IEEE / 978-0-7695-4709-1
By: Sparso, J.;
Wearout Resilience in NoCs Through an Aging Aware Adaptive Routing Algorithm
2015 / IEEE
By: Chakraborty, K.; Bhardwaj, K.; Ancajas, D.M.; Roy, S.;
Silicon Photonic Switch Fabrics in Computer Communications Systems
2015 / IEEE
By: Schares, L.; Pepeljugoski, P.; Dupuis, N.; Lee, B.G.; Schow, C.L.; Bickford, J.R.; Budd, R.;
The SpiNNaker Project
2014 / IEEE
By: Temple, S.; Galluppi, F.; Furber, S.B.; Plana, L.A.;
Multicomputers: message-passing concurrent computers
1988 / IEEE
By: Athas, W.C.; Seitz, C.L.;
A high-speed shuffle bus for VLSI arrays
1988 / IEEE
By: Hwang, J.-P.; Lin, W.-T.;
Toroidal networks
1988 / IEEE
By: Robertazzi, T.G.;
Crossover minimization in directional-coupler-based photonic switching systems
1988 / IEEE
By: Lea, C.-T.;
Analysis and design of nonequivalent multistage interconnection networks
1988 / IEEE
By: Agrawal, D.P.; Swain, N.K.; Kim, S.-C.;
Deductive fault simulation for sequential module circuits
1988 / IEEE
By: Walczak, K.;
Self-routing technique in perfect-shuffle networks using control tags
1988 / IEEE
By: Huang, S.-T.; Tripathi, S.K.;
The universality of a class of modified single-stage shuffle/exchange networks
1988 / IEEE
By: Thanawastien, S.; Srimani, P.K.;
Further results on the performance evaluation of the split channel reservation multiple access protocol ATP-2 for local area networks
1988 / IEEE
By: Papadopoulos, G.D.; Koubias, S.A.;
Realizing fault-tolerant interconnection networks via chaining
1988 / IEEE
By: Zhu, C.-Q.; Yew, P.-C.; Tzeng, N.-F.;
Continuous models for communication density constraints on multiprocessor performance
1988 / IEEE
By: Zukowski, C.A.; Glasser, L.A.;
A synthesis algorithm for reconfigurable interconnection networks
1988 / IEEE
By: Smitley, D.; Lee, I.;
Fault tolerance capabilities in multistage network-based multicomputer systems
1988 / IEEE
By: Malek, M.; Gazit, I.;
Communication performance in multiple-bus systems
1988 / IEEE
By: Yang, Q.; Zaky, S.G.;
Design and analysis of dynamic redundancy networks
1988 / IEEE
By: Siegel, H.J.; Jeng, M.;
Spanning multiaccess channel hypercube computer interconnection
1988 / IEEE
By: Dowd, P.W.; Jabbour, K.;
Analysis of gateway congestion in interconnected high-speed local networks
1988 / IEEE
By: Heath, J.R.;
Optimal assignments in broadcast networks
1988 / IEEE
By: Sinclair, J.B.;

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