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Topic: Mpsoc Architecture

Results

A framework of multi-characteristics fuzzy dynamic scheduling for parallel video processing on MPSoC architecture
2011 / IEEE / 978-1-4244-7317-5
By: Zhangqin Huang; Yibin Hou; Da Li; Chunhua Xiao;
Automatic generation of software-hardware migration in MPSoC systems
2011 / IEEE / 978-1-4244-9796-6
By: Ammari, A.C.; Smiri, K.; Fadhel, A.B.; Jemai, A.;
A framework of fuzzy dynamic scheduling for MPSoC architecture
2011 / IEEE / 978-1-61284-911-9
By: Chunhua Xiao; Zhangqin Huang; Yibin Hou; Da Li;
Graphic rendering application profiling on a shared memory MPSOC architecture
2011 / IEEE / 978-1-4577-0621-9
By: Ben Chehida, K.; David, R.; Texier, M.; Sentieys, O.;
NoC-based platform for embedded software design: An extension of the Hellfire Framework
2012 / IEEE / 978-1-4673-1036-9
By: Magalhaes, F.G.; Hessel, F.; Aguiar, A.; Filho, S.J.; Longhi, O.;
An open-source framework for heterogeneous MPSoC generation
2012 / IEEE / 978-1-4673-0186-2
By: Carara, E.A.; Lucas, C.; Wachter, E.W.; Moraes, F.G.;
Optimal loop-unrolling mechanisms and architectural extensions for an energy-efficient design of shared register files in MPSoCs
2005 / IEEE / 0-7695-2483-4
By: Atienza, D.; Ayala, J.L.; Lopez-Barrio, C.A.; Hermida, R.; Mendias, J.M.; Lopez-Vallejo, M.;
Case Study on Design Space Exploration of MPSoC architecture
2007 / IEEE / 978-89-5519-131-8
By: Sin-Chong Park; Sung-Rok Yoon;
Non-Linear Feedback Control for Energy Efficient On-Chip Streaming Computation
2006 / IEEE / 0-7803-9759-2
By: Pisano, A.; Acquaviva, A.; Carta, S.; Alimonda, A.;
Low power oriented Hardware dependent Software implementation in MPSoC architectures
2007 / IEEE / 978-1-4244-1163-4
By: Houari, A.; Bouchhima, A.; Kriaa, L.; Petrot, F.; Gligor, M.;
An MPSoC architecture for the Multiple Target Tracking application in driver assistant system
2008 / IEEE / 978-1-4244-1897-8
By: Menhaj, A.; Niar, S.; Khan, J.; Dekeyser, J.L.; Elhillali, Y.;
Multiprocessor System-on-Chip (MPSoC) Technology
2008 / IEEE
By: Jerraya, A.A.; Wolf, W.; Martin, G.;
Improving resource utilization in an multiple asynchronous ALU DSP architecture
2008 / IEEE / 978-1-4244-2920-2
By: Savaria, Y.; Tremblay, J.-P.; Mbaye, M.; Thibeault, C.;
Designing an MPSoC architecture with run-time and evolvable task decomposition and scheduling: A neural network case study
2008 / IEEE / 978-1-4244-3396-4
By: Mohammadi, S.; Fakhraie, S.M.; Vakili, S.;
Timing variation-aware task scheduling and binding for MPSoC
2009 / IEEE / 978-1-4244-2748-2
By: Taewhan Kim; HaNeul Chon;
Trace-driven workload simulation method for Multiprocessor System-On-Chips
2009 / IEEE / 978-1-6055-8497-3
By: Isshiki, T.; Satou, K.; Isomura, T.; Kunieda, H.; Dongju Li;
Efficient Scratchpad Memory Management Based on Multi-thread for MPSoC Architecture
2009 / IEEE / 978-0-7695-3825-9
By: Tianzhou Chen; Xueqing Lou; Jian Chen; Gang Wang; Wei Hu;
Global Variable Partition with Virtually Shared Scratch Pad Memory to Minimize Schedule Length
2009 / IEEE / 978-1-4244-4923-1
By: Lei Zhang; Meikang Qiu; Sha, E.H.-M.; Shaobo Liu; Fei Hu; Minyi Guo;
Multiprocessor System-on-Chip Profiling Architecture: Design and Implementation
2009 / IEEE / 978-1-4244-5789-2
By: Yuan-Ying Chang; Chung-Ta King; Po-Hui Chen; Shau-Yin Tseng;
Performance Evaluation of Cluster-Based Homogeneous Multiprocessor System-on-Chip Using FPGA Device
2009 / IEEE / 978-1-4244-4995-8
By: Gao Ming-Lun; Zhang Duo-li; Geng Luo-feng;
L2 cache modeling based on address modification for native co-simulation in systemc
2010 / IEEE / 978-1-4244-5841-7
By: Posadas, H.; Real, S.; Villar, E.;
Suitability of Hypervisor and MPSoC Architectures for the Execution Environment of an Integrated Embedded System
2011 / IEEE / 978-1-4577-0303-4
By: Iturbe, X.; Martinez, I.; Azkarate-askasua, M.; Obermaisser, R.;
An energy-aware methodology for mapping and scheduling of concurrent applications in MPSoC architectures
2011 / IEEE / 978-964-463-428-4
By: Rajaei, R.; Vahdat, B.V.; Hessabi, S.;

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