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Topic: Logic Simulation

Results

Standard cell VLSI design: A tutorial
1985 / IEEE
By: Ganesan, A.; Kessler, A.J.;
Parallel Logic Simulation: Myth or Reality?
2012 / IEEE
By: Browy, C.; Kai-hui Chang;
Majority Voter Full Characterization for Nanomagnet Logic Circuits
2012 / IEEE
By: Vacca, M.; Zamboni, M.; Graziano, M.;
Studying the influence of chip temperatures on timing integrity
2011 / IEEE / 978-1-4577-1490-0
By: Timar, A.; Rencz, M.;
A simulation of basic logic circuit based on ternary quantum-dot cellular automata
2011 / IEEE / 978-988-17255-9-2
By: Pei Tai-Yi; Ying Shi-Yan; Xiao Lin-Rong;
Self-Programmable Multipurpose Digital Filter Design Based on FPGA
2011 / IEEE / 978-1-4244-7255-0
By: Hu Wenjing; Li Waiyun; Zhang Guoyun;
Logic simulation acceleration based on GPU
2011 / IEEE / 978-83-932075-2-7
By: Fan Xiaoya; Kai Yaowen; Wei Tingcun; Zhang Yuxuan; Zhao Lili; Zhang Meng;
The reliability simulation analysis of a multi-unit cold stanby system with unreliable switch
2011 / IEEE / 978-1-4577-0321-8
By: Sun Yufeng; Fan Xubin;
Circuit impact of device and interconnect parasitics in a complementary low-voltage organic thin-film technology
2011 / IEEE / 978-1-4577-0430-7
By: Zaki, T.; Klauk, H.; Zschieschang, U.; Ante, F.; Butschke, J.; Burghartz, J.N.; Richter, H.; Letzkus, F.;
Applying verification intention for design customization via property mining under constrained testbenches
2011 / IEEE / 978-1-4577-1954-7
By: Sy-Yen Kuo; Kai-Hui Chang; Chia-Wei Chang; Chih-Neng Chung;
A novel simulation environment enabling multilevel power estimation of digital systems
2011 / IEEE / 978-2-35500-016-4
By: Poppe, A.; Nagy, G.;
An Improved F-M Partitioning Algorithm in Parallel Logic Simulation
2011 / IEEE / 978-1-4577-1788-8
By: Yuzhuo Fu; Jiafang Wang;
Efficient BDD-based Fault Simulation in Presence of Unknown Values
2011 / IEEE / 978-1-4577-1984-4
By: Kochte, M.A.; Wunderlich, H.; Xiaoqing Wen; Miyase, K.; Kundu, S.;
A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique
2011 / IEEE / 978-1-4577-1880-9
By: Kumar, C.I.; Parashar, S.; Pattanaik, M.; Mahor, V.; Chouhan, A.;
The AES Encryption and Decryption Realization Based on FPGA
2011 / IEEE / 978-1-4577-2008-6
By: Luan Lan;
A scan pattern debugger for partial scan industrial designs
2012 / IEEE / 978-1-4577-2145-8
By: Sengupta, S.; Misra, S.K.; Chandrasekar, K.; Hsiao, M.S.;
Don't let the X-bugs bite: Conquer elusive X-propagation issues early! Get them before they get you!
2011 / IEEE / 978-1-61284-193-9
By: Jin Zhang; Piper, L.;
Failure Analysis on Open Defect with Logic Time Sequence Analysis and Simulation Experiment Method
2012 / IEEE / 978-1-4577-2120-5
By: Winter Wang; Gaojie Wen; Diwei Fan; Chunlei Wu; Miao Wu; Li Tian;
Exploiting binary translation for fast ASIP design space exploration on FPGAs
2012 / IEEE / 978-1-4577-2145-8
By: Meloni, P.; Pomata, S.; Lindwer, M.; Raffo, L.; Tuveri, G.;
Improving gate-level simulation accuracy when unknowns exist
2012 / IEEE / 978-1-4503-1199-1
By: Browy, C.; Kai-Hui Chang;
Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case
2012 / IEEE / 978-1-4673-1605-7
By: Antonopoulos, C.D.; Bellas, N.; Novo, D.; Purnaprajna, M.; Karakonstantis, G.; Owaida, M.; Falcao, G.; Ienne, P.; Burg, A.;
Logic simulation and fault collapsing with shared structurally synthesized bdds
2014 / IEEE
By: Ubar, Raimund; Mironov, Dmitri; Raik, Jaan;
Automated methods for eliminating X bugs
2014 / IEEE
By: Chang, Kai-Hui; Browy, Chris; Liu, Yen-Ting;
Virtual laboratory for educational environments
2014 / IEEE
By: Barata, Manuel; Miguens Matutino, Pedro; Dias, Fabio;
Fast functional simulation: an incremental approach
1988 / IEEE
By: Choi, K.; Blank, T.; Hwang, S.Y.;
Parallel logic simulation on general purpose machines
1988 / IEEE / 0-8186-0864-1
By: Soule, L.; Blank, T.;
Design of multilevel mixed-mode simulator for LSI/VLSI circuits
1988 / IEEE
By: Dabrowski, J.;
Electrical-logic simulation and its applications
1989 / IEEE
By: Seung Ho Hwang; Young Hwan Kim; Newton, A.R.;
Introducing VLSI computer-aided design into the EE curriculum: a case study
1989 / IEEE
By: Bass, S.C.; Lindenlaub, J.C.; O'Keefe, M.T.; Wahlen, T.P.;
Transparent logic modeling in VHDL
1990 / IEEE
By: DeGroat, J.E.;
Improved test generation for high-activity circuits
1990 / IEEE
By: Kim, K.; Saluja, K.;
Switch-level simulation using dynamic graph algorithms
1991 / IEEE
By: Adler, D.;
Logic simulation with interval-labelled net model
1989 / IEEE
By: Cheung, Y.S.; Chiu, P.P.K.;
A new architecture for fast modular multiplication
1989 / IEEE
By: Chin-Hsing Chen; Jau-Yien Lee; Erl-Huei Lu; Yeong-Jiunn Juang;
SYMCELL-a symbolic standard cell system
1991 / IEEE
By: Ramachandran, K.; Kwan, A.F.; Deutsch, D.N.; Daly, D.F.; Cordell, R.R.;
Design Test: a solution to the problems of ASIC verification
1989 / IEEE
By: Peters, M.; Bashford, P.; Allingham, D.; Vendl, D.;
A VHSIC compatible CMOS/SOS cell family
1988 / IEEE
By: Martinez, M.A.; Polkinghorn, R.W.;
Why is less information from logic simulation more useful in fault simulation?
1990 / IEEE / 0-8186-9064-X
By: Swaminathan, A.; Krishnamurthy, B.; Park, S.; Akers, S.B.;
Modeling and enhancing virtual memory performance in logic simulation
1988 / IEEE / 0-8186-0869-2
By: Kuban, J.; Smith, S.P.;
Race detection for two-phase systems
1990 / IEEE / 0-8186-2055-2
By: Grodstein, J.; Marino, S.; Montanaro, J.;
Exploitation of periodicity in logic simulation of synchronous circuits
1990 / IEEE / 0-8186-2055-2
By: Ulrich, E.; Bischoff, G.; Razdan, R.;
Performance estimation in a massively parallel system
1990 / IEEE / 0-8186-2056-0
By: Chakradhar, S.T.; Agrawal, V.D.;
Software architecture of universal hardware modeler
1990 / IEEE / 0-8186-2024-2
By: Stump, H.E.; Kelly, N.F.;
A parallel algorithm for logic simulation on transputer networks
1991 / IEEE / 0-8186-2170-2
By: Srinivas, S.; Patnaik, L.M.; Paulraj, A.; Basu, A.;
Analysis of parallel mixed-mode simulation algorithms
1991 / IEEE / 0-8186-9167-0
By: Chamberlain, R.D.; Franklin, M.A.;
A VLSI design system for teaching introduction to microelectronics
1992 / IEEE
By: Sicard, E.; Kinashita, K.; Rubio, A.;
A mixed-mode simulator for digital/analog VLSI circuits using an efficient timing simulation approach
1991 / IEEE / 0-7803-0050-5
By: Jun, Y.-H.; Hajj, I.N.;
Performance analysis of synchronized iterative algorithms on multiprocessor systems
1992 / IEEE
By: Chakradhar, S.T.; Agrawal, V.D.;
Two new techniques for compiled multi-delay simulation
1992 / IEEE / 0-7803-0494-2
By: Lee, Y.-S.; Maurer, P.M.;
Automatic formal verification of Cathedral-II circuits from transistor switch level implementation up to high level behavioral specifications by the SFG-tracing methodology
1992 / IEEE / 0-8186-2645-3
By: Genoe, M.; De Man, H.; Proesmans, F.; Verlind, E.; Claesen, L.;
VLSI logic and fault simulation on general-purpose parallel computers
1993 / IEEE
By: Abraham, J.A.; Damiano, R.F.; Saab, D.G.; Mueller-Thuns, R.B.;
An associative memory approach to parallel logic event-driven simulation
1992 / IEEE / 0-8186-2760-3
By: Dalton, D.;
ASIC library qualification: criteria and procedure
1992 / IEEE / 0-8186-2845-6
By: Takayoshi, H.; Konishi, K.; Kawamoto, E.; Fudanuki, N.; Horikawa, K.;
Intractability in linear switch-level simulation
1993 / IEEE
By: Huang, L.P.; Bryant, R.E.;
Test pattern generation system for delay faults using a high speed simulation processor 'SP'
1992 / IEEE / 0-7803-0623-6
By: Izuta, Y.; Hirose, F.;
Logic simulation of RSFQ circuits
1993 / IEEE
By: Krasniewski, A.;
Bit-serial multiplier based on Josephson latching logic
1993 / IEEE
By: Moopenn, A.; Chan, H.W.; Lewis, M.J.; Arambula, E.R.;
A compact simulation engine with flexible logic model expansion
1992 / IEEE / 0-7803-0734-8
By: Tomita, M.; Suganuma, N.; Hirano, K.;
A comparative analysis of different fault simulation techniques for VLSI circuits testing
1991 / IEEE / 0-87942-688-8
By: de la Torre, E.; Riesgo, T.; Torroja, Y.; Uceda, J.;
Gateways: a technique for adding event-driven behavior to compiled simulations
1994 / IEEE
By: Maurer, P.M.; Yun Sik Lee;
Improved modelling and characterization system for logic simulation
1992 / IEEE / 0-7803-0768-2
By: Misheloff, M.N.;
Minimizing testing time in scan-path architecture
1992 / IEEE / 0-7803-0510-8
By: Edirisooriya, S.; Edirisooriya, G.;
Test generation for logic simulation based on functional graph
1992 / IEEE / 0-7803-0510-8
By: Jiang, H.; Tomita, M.;
A field programmable accelerator for compiled-code applications
1993 / IEEE / 0-8186-3890-7
By: Wong, D.H.; van Ierssel, M.H.; Lewis, D.M.;
Logic simulation using an asynchronous parallel discrete-event simulation model on a SIMD machine
1994 / IEEE / 0-8186-4990-9
By: Seth, S.; Sylwester, D.; Payne, M.; Gowen, L.;
A mathematical level/strength model for synthesizing STD-LOGIC-1164 values
1994 / IEEE / 0-8186-6215-8
By: Vellenga, J.H.;
Logic and fault simulation by cellular automata
1994 / IEEE / 0-8186-5410-4
By: Yih-Lang Li; Cheng-Wen Wu;
An analysis of parallel synchronous and conservative asynchronous logic simulation schemes
1994 / IEEE / 0-8186-6427-4
By: Mahmood, A.; Baker, W.I.;
Automatic program generator for simulation-based processor verification
1994 / IEEE / 0-8186-6690-0
By: Nakata, T.; Kowatari, S.; Iwashita, H.; Hirose, F.;
Hardware-accelerated parallel-pattern/multiple-fault-propagation concurrent fault simulation
1994 / IEEE / 0-8186-6690-0
By: Hahn, W.; Hagerer, A.;
Method for acceleration of logic simulations
1994 / IEEE / 0-7803-1862-5
By: Fukazawa, Y.; Sakakura, M.;
Logic simulation using T-algorithm on network of workstations
1994 / IEEE / 0-7803-1862-5
By: Sundaram, S.; Srinivas, M.K.;
Functional timing analysis using ATPG
1993 / IEEE / 0-8186-3410-3
By: Ashar, P.; Rothweiler, S.; Malik, S.;
Massively parallel array processor for logic, fault, and design error simulation
1995 / IEEE / 0-8186-6445-2
By: Scott Fehr, E.; Szygenda, S.A.; Hur, Y.; Ott, G.E.; Sungho Kang;
A field programmable accelerator for compiled-code applications
1993 / IEEE / 0-8186-4230-0
By: van Ierssel, M.H.; Lewis, D.M.; Wong, D.H.;
Design methodology for GMICRO/500 TRON microprocessor
1993 / IEEE / 0-8186-4230-0
By: Narita, S.; Kawasaki, I.; Uchiyama, K.; Arakawa, F.;
The PowerPC 601 design methodology
1993 / IEEE / 0-8186-4230-0
By: Schiffli, M.; Brodnax, T.; Watson, F.;
Process combination to increase event granularity in parallel logic simulation
1995 / IEEE / 0-8186-7074-6
By: Wilsey, P.A.; McBrayer, T.J.;
Integrating logic simulation and dependency modeling
1993 / IEEE / 0-7803-0646-5
By: Debany, W.H.; Unkle, C.R.; Daskiewich, D.E.;
Clustered time warp and logic simulation
1995 / IEEE / 0-8186-7120-3
By: Tropper, C.; Avril, H.;
ASIC manufacturability simulation
1993 / IEEE / 0-7803-1375-5
By: Chin-Fu Chen; Foong-Charn Chang; Chadha, R.; Eiseman, J.;
LOCSTEP: a logic simulation based test generation procedure
1995 / IEEE / 0-8186-7079-7
By: Reddy, S.M.; Pomeranz, I.;
Logic, fault, and design error simulation based on an integrated hardware array
1995 / IEEE / 0-7803-2492-7
By: Szygenda, S.A.; Hur, Y.;
Hardware-accelerated concurrent fault simulation: eventflow computing versus dataflow computing
1995 / IEEE / 0-8186-7129-7
By: Hagerer, A.; Hahn, W.; Kandlbinder, R.;
Deterministic test generation for non-classical faults on the gate level
1995 / IEEE / 0-8186-7129-7
By: Alt, J.; Mahlstedt, U.; Hollenbeck, I.;
An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctuation
1995 / IEEE / 4-930813-67-0
By: Kinoshita, M.; Iwabuchi, M.; Yokomizo, G.; Miyama, M.;
On finding functionally identical and functionally opposite lines in combinational logic circuits
1996 / IEEE / 0-8186-7228-5
By: Reddy, S.M.; Pomeranz, I.;
Statistical path delay fault coverage estimation for synchronous sequential circuits
1996 / IEEE / 0-8186-7228-5
By: Srinivas, M.K.; Agrawal, V.D.; Bushnell, M.L.; Pappu, L.;
An architecture for a verilog hardware accelerator
1996 / IEEE / 0-8186-7431-8
By: Burns, C.;
Implementation of synthesized digital systems with VHDL
1995 / IEEE / 0-7803-2624-5
By: Ng, L.S.; Jong, C.C.;
A power modelling and characterization method for logic simulation
1995 / IEEE / 0-7803-2584-2
By: McNelly, A.J.; Sarin, H.K.;
Equation based timing: methodology and model for cell libraries
1995 / IEEE / 0-7803-2584-2
By: Brown, K.D.; Cannon, R.Y.;
Dual threshold delay model for nonlinear device characterization
1995 / IEEE / 0-7803-2584-2
By: Tomita, Y.; Edamatsu, H.; Yamaguchi, R.; Iwanishi, N.;
Application of synthesis to support hardware emulation
1995 / IEEE / 0-8186-7100-9
By: Nguyen, H.N.; D'Hoe, M.; Gressus, Y.;
Test generation and logic/fault simulation of programmable logic arrays: optimized partitioning techniques for parallel processing
1994 / IEEE / 0-7803-2428-5
By: Cruz, A.; Sarma, D.;
Logic synthesis for a single large look-up table
1995 / IEEE / 0-8186-7165-3
By: Hirose, F.; Fujita, M.; Murgai, R.;
A comparison of test requirements, methods, and results for seven MCM products
1995 / IEEE / 0-7803-2992-9
By: Flint, A.;
Hierarchical functional fault simulation for high-level synthesis
1995 / IEEE / 0-7803-2992-9
By: Tyszer, J.; Rajski, J.; Kassab, M.;
Using the right tools and techniques leads to successful testing of MCMs
1995 / IEEE / 0-7803-2992-9
By: Flint, A.;
Compiled code dynamic worst case timing simulation tracking multiple causality
1995 / IEEE / 0-7803-2992-9
By: Varma, K.K.;

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