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Topic: Hardware Description Languages

Results

P-functions: A new tool for the analysis and synthesis of binary programs
1981 / IEEE
By: Thayse, A.;
A low energy adaptive hardware for H.264 multiple reference frame motion estimation
2011 / IEEE
By: Aysu, A.; Hamzaoglu, I.; Sayilar, G.;
Energy reduction techniques for H.264 deblocking filter hardware
2011 / IEEE
By: Hamzaoglu, I.; Parlak, M.; Adibelli, Y.;
Data Archival to SD Card Via Hardware Description Language
2011 / IEEE
By: Todakar, V.S.; Elkeelany, O.;
A Behavioral Circuit Model of Active-Matrix Liquid Crystal Displays for Optical Response Simulation
2012 / IEEE
By: Chansoo Park; Youngmin Cho; Seung-Woo Lee; Seung-Hyuck Lee; Jong-Man Kim;
Magnetic Tunnel Junction-Based Spin Register for Nonvolatile Integrated Circuits
2012 / IEEE
By: Yanfeng Jiang; Jian-Ping Wang; Harms, J.D.;
VHDL-AMS to Support DAE-PDE Coupling and Multilevel Modeling
2012 / IEEE
By: Rezgui, A.; Delinchant, B.; Gerbaud, L.;
Performance of Cooled PWO Scintillators With Signal-Sampling Readout
2012 / IEEE
By: Tambave, G.; Lemmens, P.J.J.; Kavatsyuk, M.; Guliyev, E.; Lohner, H.;
Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course
2012 / IEEE
By: Vazquez, M.; Marone, J.A.; Todorovich, E.;
MS2SV: Environment for translation of Matlab / Simulink models to VHDL-AMS models
2011 / IEEE
By: da Silva, A.C.R.; Grout, I.A.;
A Technique for Test Coverage Closure Using GoldMine
2012 / IEEE
By: Vasudevan, S.; Tuohy, W.; Sheridan, D.; Lingyi Liu;
An Explicit Linearized State-Space Technique for Accelerated Simulation of Electromagnetic Vibration Energy Harvesters
2012 / IEEE
By: Kazmierski, T.J.; Merrett, G.V.; Al-Hashimi, B.M.; Wang, L.;
synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs
2012 / IEEE
By: Patel, H.D.; Sinha, R.;
Assertion Aware Sampling Refinement: A Mixed-Signal Perspective
2012 / IEEE
By: Dasgupta, P.; Mukherjee, S.;
Static and Dynamic Modeling of Single-Electron Memory for Circuit Simulation
2012 / IEEE
By: Bounouar, M.; Guilmain, M.; Beaumont, A.; Wei Xuan; Baboux, N.; Calmon, F.; Drouin, D.; Etzkorn, J.;
Accurate Compact Modeling for Sub-20-nm nand Flash Cell Array Simulation Using the PSP Model
2012 / IEEE
By: Kihwan Choi; Jongwook Jeon; Wookghee Hahn; Myounggon Kang; Il Han Park; Sunghee Yun; Chilhee Chung; Young-Kwan Park; Keun-Ho Lee; Gi-Young Yang;
SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience
2012 / IEEE
By: Seligman, E.; Korchemny, D.; Bustan, D.; Jin Yang;
That's not our job! [Standards]
2012 / IEEE
By: Krolikoski, S.;
Modeling of Wireless Sensor Nodes Powered by Tunable Energy Harvesters: HDL-Based Approach
2012 / IEEE
By: Ayala-Garcia, I.N.; Weddell, A.S.; Al-Hashimi, B.M.; Wang, L.; Merrett, G.V.; Kazmierski, T.J.;
FPGA Implementation of BASK-BFSK-BPSK Digital Modulators [Testing Ourselves]
2012 / IEEE
By: Erdogan, C.; Minaei, S.; Myderrizi, I.;
An Overview of Open SystemC Initiative Standards Development
2012 / IEEE
By: Bhattacharya, B.; Wieman, T.; Vanthournout, B.; Schroder, C.; Jeremiassen, T.;
Physical Parameter-Based SPICE Models for InGaZnO Thin-Film Transistors Applicable to Process Optimization and Robust Circuit Design
2012 / IEEE
By: Hyuck-In Kwon; Dong Myong Kim; Yun Seop Yu; Yongsik Kim; Sungchul Kim; Yong Woo Jeon; Dae Hwan Kim;
Characterization of Analog Circuits Using Transfer Function Trajectories
2012 / IEEE
By: Gielen, G.; De Jonghe, D.;
Functional Test-Sequence Grading at Register-Transfer Level
2012 / IEEE
By: Patil, S.; Jas, A.; Chakrabarty, K.; Hongxia Fang; Tirumurti, C.;
A Comparison of Simulation and Hardware-in-the- Loop Alternatives for Digital Control of Power Converters
2012 / IEEE
By: Garrido, J.; de Castro, A.; Sanchez, A.;
VHDL Implementation of a Flexible and Synthesizable FFT Processor
2012 / IEEE
By: Correa, I.S.; Costa, J.C.W.A.; Klautau, A.; Freitas, L.C.;
Architectural Characterization and Code Compression in Embedded Processors
2012 / IEEE
By: Dias, W.R.A.; da S Barreto, R.; Moreno, E.D.;
Architectural exploration of Forward 4� Hadamard Transform applied to H.264/AVC video compression standard
2009 / IEEE / 978-1-4577-0236-5
By: Silva, A.M.C.; da Costa, E.A.C.; de Almeida, S.J.M.; Altermann, J.S.;
Efficient hardware design for the upsampling in the H.264/SVC scalable video coding extension
2009 / IEEE / 978-1-4577-0236-5
By: Bampi, S.; Susin, A.A.; da Silva, T.L.; Agostini, L.V.; Rediess, F.K.;
GenerateRCS: A high-level design tool for generating reconfigurable computing systems
2009 / IEEE / 978-1-4577-0236-5
By: Becker, J.; Luhmann, J.; Gohringer, D.;
Efficient single event upset simulations of a tolerant PD SOI CMOS D Flip-Flop
2009 / IEEE / 978-1-4577-0493-2
By: Kilchytska, V.; Alvarado, J.; Flandre, D.; Berger, G.;
Modelling of �-radiation effects in bipolar transistors with VHDL-AMS
2009 / IEEE / 978-1-4577-0493-2
By: De Cock, W.; Van Uffelen, M.; Leroux, P.; Versmissen, H.;
A new method for significance map decoding acceleration in the CABAD regular hardware engine
2009 / IEEE / 978-1-4577-0236-5
By: Bampi, S.; Depra, D.A.;
Functional Coverage Driven Verification for TAU-MVBC
2010 / IEEE / 978-1-4244-9954-0
By: Zhijun Zhang; Jian Wu; Aihong Yao;
Hierarchical generation of pin accurate SystemC models based on RF circuit schematics
2010 / IEEE / 978-1-4244-8997-8
By: Zhimiao Chen; Yifan Wang; Heinen, S.;
Design and modeling of a successive approximation ADC for the electrostatic harvester of vibration energy
2010 / IEEE / 978-1-4244-8997-8
By: Iskander, R.; Galayko, D.; Dudka, A.; Khalil, R.; Basset, P.;
Fault injection in mixed-signal environment using behavioral fault modeling in Verilog-A
2010 / IEEE / 978-1-4244-8997-8
By: Miremadi, S.-G.; Ahmadian, S.-M.;
A parallel processing architecture for FSS block-matching motion estimation
2011 / IEEE / 978-1-4577-0411-6
By: Dhahri, S.; Tourki, R.; Zitouni, A.;
The future of the device integration: Field device integration
2011 / IEEE / 978-1-4244-9698-3
By: Qiao Li; Feng Liu;
Design and implementation of the vehicle slide angle estimator based on FPGA
2011 / IEEE / 978-988-17255-9-2
By: Xie Xiaohua; Jia Zengben; Liu Tong; Lian Xi;
FPGA controller for rearrangeable Log2(N, 0, p) fabrics with an even number of stages
2011 / IEEE / 978-1-4244-8456-0
By: Michalski, M.; Kabacinski, W.;
A Cluster Timing Algorithm for drift chambers readout electronics
2011 / IEEE / 978-1-4577-0624-0
By: Cappelli, L.; Grancagnolo, F.; Creti, P.;
Three-phase inverter circuit PWM controller which is based on CPLD
2011 / IEEE / 978-1-4244-9439-2
By: Ming Zhang; Qiong Wu; Liyu Tao;
An FPGA implementation and performance evaluation of the seed block cipher
2011 / IEEE / 978-1-4577-0274-7
By: Kitsos, P.; Skodras, A.N.;
The Xilinx Design Language (XDL): Tutorial and use cases
2011 / IEEE / 978-1-4577-0642-4
By: Koch, D.; Beckhoff, C.; Torresen, J.;
Evaluating coverage collection using the VEasy functional verification tool suite
2011 / IEEE / 978-1-4577-1490-0
By: Kastensmidt, F.L.; Haacke, P.A.; Pagliarini, S.N.;
Are logic synthesis tools robust?
2011 / IEEE / 978-1-4503-0636-2
By: Sangiovanni-Vincentelli, A.; Kuehlmann, A.; Welp, T.; Puggelli, A.;
Fault-tolerance assessment and enhancement in SoCWire interface: A system-on-chip wire
2011 / IEEE / 978-1-4577-1056-8
By: Salamat, R.; Zarandi, H.R.;
The infrared remote system design based on FPGA
2011 / IEEE / 978-1-61284-774-0
By: Zhibo Xie; Jindi Dong;
Designing and analyzing a SpaceWire router IP for soft errors detection
2011 / IEEE / 978-1-4577-1490-0
By: Chielle, E.; Chipana, R.; Tarrillo, J.; Kastensmidt, F.L.;
A cache based algorithm to predict HDL modules faults
2011 / IEEE / 978-1-4577-1490-0
By: Silva, T.S.F.; Nacif, J.A.M.; Coelho, C.N.; Fernandes, A.O.; Vieira, A.B.; Vieira, L.F.M.;
NoCmodel: An extensible framework for Network-on-Chips modeling
2011 / IEEE / 978-1-4577-0642-4
By: Lazaro, J.; Zuloaga, A.; Astarloa, A.; Diaz, O.; Jimenez, J.;
Single Electron Transistor analytical model for hybrid circuit design
2011 / IEEE / 978-1-61284-137-3
By: Bounouar, M.A.; Calmon, F.; Beaumont, A.; Guilmain, M.; Xuan, W.; Ecoffey, S.; Drouin, D.;
Fast prototyping environment for embedded reconfigurable units
2011 / IEEE / 978-1-4577-0642-4
By: Lagadec, L.; Picard, D.;
Optimal design of the serial data receiving path
2011 / IEEE / 978-988-17255-9-2
By: Miao Ling-Juan; Xu Li; Shen Jun;
Automatic generation of graphical user interfaces for VHDL based controllers
2011 / IEEE / 978-1-4244-9312-8
By: Moutinho, F.; Gomes, L.; Pereira, F.;
Hardware-in-the-loop simulation of FPGA embedded processor based controls for power electronics
2011 / IEEE / 978-1-4244-9312-8
By: Urriza, I.; Jimenez, O.; Lucia, O.; Artigas, J.I.; Navarro, D.; Barragan, L.A.;
Study on design method of boundary-scan circuit architecture based on Verilog language
2011 / IEEE / 978-1-4244-9439-2
By: Luo Jian; Xu Lei; Zhou Yin; Chen Shengjian;
All DPLLs based on fuzzy PI control algorithm
2011 / IEEE / 978-1-4244-9439-2
By: Hua Yuan; Yong Li; Zhongze Chen; Changhong Shan;
Backplane bus controller implementation in Fpga for hard real time control systems
2011 / IEEE / 978-1-61284-486-2
By: Waqar, A.; Muhammad, A.H.; Yian Zhu; Abbas, G.G.; Jianfeng An;
VLSI implementation of synchronizer and pipelined CORDIC in OFDM receiver for fourth generation wireless LAN applications
2011 / IEEE / 978-1-61284-486-2
By: Gudheti, R.R.; Penubolu, S.R.;
Implementation of data transfer and synchronous pulse operation for ARINC 659
2011 / IEEE / 978-1-61284-486-2
By: Jianfeng An; Waqar, A.; Abbas, G.G.; Xiaoya Fan; Muhammad, A.H.;
Design of the ADPCM synthetic voice chip
2011 / IEEE / 978-1-4577-0536-6
By: Rongjian Zhao; Shuxin Li; Ning Tang;
Design method of viterbi decoding of convolutional code based on VHDL
2011 / IEEE / 978-1-61284-486-2
By: Xiao Cheng; Zhang Zengliang;
The research about the torque motor controller of automobile electromechanical braking system based on FPGA
2011 / IEEE / 978-1-4244-9600-6
By: Xu Jin; Li Min; Liu Zhuo;
A ROM-less direct digital frequency synthesizer based on a scaling-free CORDIC algorithm
2011 / IEEE / 978-1-4577-0399-7
By: Yi-Jiang Cao; Tze-Yun Sung; Yang Wang;
A FPGA LED controller for SoC
2011 / IEEE / 978-1-61284-088-8
By: Xiao Luo; Limin Liu;
Optimized design and simulation on a single-precision-floating divider
2011 / IEEE / 978-1-4577-0536-6
By: Zhi-gang Liu; Rong Lin;
Design of high-precision FFT based on VHDL and analysis of code coverage
2011 / IEEE / 978-1-61284-088-8
By: Jun Cheng;
The Design and Simulation of Frequency Divider Based on VHDL
2011 / IEEE / 978-1-4577-0860-2
By: Wei Yong; Yu Yaping; Zhao Jincai; Du Yanhong; Liu Yuan;
Design of three-lift controller based on FPGA
2011 / IEEE / 978-1-61284-088-8
By: Yujun Bao; Xiaoyan Jiang;
VHDL Modelling of Fixed-point DWT for the Purpose of EMG Signal Denoising
2011 / IEEE / 978-1-4577-0975-3
By: Ahsan, M.R.; Khalifa, O.O.; Ibrahimy, M.I.;
A Self Learning VLSI Lab along with Web-Based Platform to Design Schematics and Layouts
2011 / IEEE / 978-0-7695-4534-9
By: Anwar, M.; Azeemuddin, S.; Sharma, S.;
The design and simulation of array multiplier improved with pipeline techniques
2011 / IEEE / 978-1-61284-088-8
By: Jin-qiu Xiao; Zhong-ye Yang;
Towards Denotational Semantics for Verilog in PVS
2011 / IEEE / 978-1-4577-0781-0
By: Jian Guo; Si Liu; Huibiao Zhu; Han Zhu;
The study of the measured frequency in EPM3128 based on the VHDL language
2011 / IEEE / 978-1-4244-9600-6
By: Ding Qian; Lian Ya-fei; Zhang Zi-sheng; Li Guan; Ji Ying-chao;
Hardware implementation on a Xilinx Virtex4
2011 / IEEE / 978-1-4244-9796-6
By: Maaref, H.; Halim, S.; Abdelaziz, A.; Aymen, M.;
Five-level five-phase PWM signal generation using FPGA
2011 / IEEE / 978-1-4577-0419-2
By: Okaro, M.; Adhikari, P.;
HDL to SP conversion containing interconnect effects using SAD matrix
2011 / IEEE / 978-1-61284-857-0
By: Golzar, M.G.; Tajozzakerin, H.;
Development of FPGA-based arithmetic module in CNC system
2011 / IEEE / 978-1-61284-722-1
By: Baosheng Wang; Mulan Wang; Xiaoxia Li; Xinghua Zhu;
An automatically generated VHDL-code of a Delta-Sigma-Modulator
2011 / IEEE / 978-83-932075-2-7
By: Linkesch, W.; Spilka, R.; Ostermann, T.;
DVB-CSA encryption in digital hardware
2011 / IEEE / 978-83-932075-2-7
By: Marucha, P.W.; Szecowka, P.M.;
FeatureVerilog: Extending Verilog to Support Feature-Oriented Programming
2011 / IEEE / 978-1-61284-425-1
By: Tan Qingping; Ye Jun; Cao Guorong; Li Tun;
Combining various modeling techniques for power electronic systems in automotive applications
2011 / IEEE / 978-83-932075-2-7
By: Szelest, M.; Niemiec, H.;
Modeling a quantum processor using the QRAM model
2011 / IEEE / 978-1-4577-0253-2
By: Elrefaei, H.; El-Kharashi, M.W.; Elhoushi, M.;
A scheduling approach for packet-switched on-chip networks
2011 / IEEE / 978-1-4244-9796-6
By: Bennour, I.E.; Zeghid, M.; Salah, Y.; Tourki, R.;
Quasi-delay-insensitive compiler: Automatic synthesis of asynchronous circuits from verilog specifications
2011 / IEEE / 978-1-61284-857-0
By: Kwen-Siong Chong; Rong Zhou; Chang, J.S.; Bah-Hwee Gwee;
Modelling a fast BLAS level-1 inspired vectorized FPU for ARM devices
2011 / IEEE / 978-1-61284-857-0
By: Vigliar, M.; Del Mastro, G.; D'Auria, A.; Raiconi, G.;
A comprehensive physics-based power MOSFET model in VHDL-AMS for circuit simulations
2011 / IEEE / 978-90-75815-14-6
By: Rose, M.; Gohler, L.;
Study of correlations among noise sources in �� modulator models
2011 / IEEE / 978-1-61284-857-0
By: Jimenez, M.; Bula, C.D.;
Reuse of flexible hardware modules for practical implementation of intra H.264/SVC video encoder
2011 / IEEE / 978-1-61284-857-0
By: Kintschner, R.; Susin, A.A.; Husemann, R.; Roesler, V.; Valdeni, J.;
A low-power high-linearity symmetrical readout circuit for capacitive sensors
2011 / IEEE / 978-1-61284-857-0
By: Ziqiang Wang; Kaimin Zhou; Zhihua Wang; Chun Zhang; Fule Li;
The design of code-decode circuits in PI-BUS interface unit chip and its software realization
2011 / IEEE / 978-1-61284-181-6
By: Liu Yan;
Development of a reliable GUI for DiaHDL: A web-based VHDL code generator
2011 / IEEE / 978-1-4577-0752-0
By: Thoyib, W.; Susanti, A.R.D.; Schumann, T.;
Random number generation based on digital differential chaos
2011 / IEEE / 978-1-61284-857-0
By: Radwan, A.G.; Zidan, M.A.; Salama, K.N.;
Design and implement of the digital storage oscilloscope card based on VHDL
2011 / IEEE / 978-1-4244-8161-3
By: He Zhiqiang; Zhang Jingzhi; Feng Guonan;
Implementation of a LMS filter on FPGA employing extremeDSP and smart IP-core design
2011 / IEEE / 978-1-4244-8161-3
By: Liu Xuebin; Wang Yaqin; Hu Bingliang;
An iterative real-time nonlinear electromagnetic transient solver on FPGA
2011 / IEEE / 978-1-4577-1002-5
By: Yuan Chen; Dinavahi, V.;
Implementation of a QPSK system on FPGA
2011 / IEEE / 978-1-4577-1974-5
By: Gontean, A.S.; Popescu, S.O.; Ianchis, D.;
High performance Haar Wavelet transform architecture
2011 / IEEE / 978-1-4577-0618-9
By: Altermann, J.; Almeida, S.; Costa, E.;

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