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Topic: Fpga

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A low energy adaptive hardware for H.264 multiple reference frame motion estimation
2011 / IEEE
By: Aysu, A.; Hamzaoglu, I.; Sayilar, G.;
Parallel pipelined array architectures for real-time histogram computation in consumer devices
2011 / IEEE
By: Wen-Chung Kao; Huerta, P.; Sherratt, R.S.; Cadenas, J.O.;
Product spotlights
2011 / IEEE
Are Field-Programmable Gate Arrays Ready for the Mainstream?
2011 / IEEE
By: Stitt, G.;
Automated Range and Precision Bit-Width Allocation for Iterative Computations
2011 / IEEE
By: Kinsman, A.B.; Nicolici, N.N.;
Energy reduction techniques for H.264 deblocking filter hardware
2011 / IEEE
By: Hamzaoglu, I.; Parlak, M.; Adibelli, Y.;
Layout-Aware Multi-Cell Upsets Effects Analysis on TMR Circuits Implemented on SRAM-Based FPGAs
2011 / IEEE
By: Bocquillon, A.; Panariti, A.; Violante, M.; Sterpone, L.; Miller, F.; Gerardin, S.; Paccagnella, A.; Manuzzato, A.; Buard, N.;
High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulations
2011 / IEEE
By: Aracil, J.; Gomez-Arribas, F.J.; Gonzalez, I.; Lopez-Buedo, S.; Sutter, G.; Sanchez-Roman, D.; Palacios, F.;
FPGA-Based Particle Recognition in the HADES Experiment
2011 / IEEE
By: Kuhn, W.; Ming Liu; Jantsch, A.; Zhonghai Lu;
An FPGA-Based Embedded Robust Speech Recognition System Designed by Combining Empirical Mode Decomposition and a Genetic Algorithm
2012 / IEEE
By: Shing-Tai Pan; Xu-Yu Li;
A Project-Based Learning Approach to Programmable Logic Design and Computer Architecture
2012 / IEEE
By: Kellett, C.M.;
Implementation and Co-Simulation of Hybrid Pilot-Aided Channel Estimation With Decision Feedback Equalizer for OFDM Systems
2012 / IEEE
By: Cosmas, J.; Maple, C.; Li-Ke Huang; Yue Zhang; Wei Li;
Reconfigurable high-speed platform: shifting the paradigm in education, research and engineering
2012 / IEEE
By: Vanderhorn, N.; Jin-Wei Tioh; Somani, A.K.; Weber, R.J.; Mina, M.;
Trigger Performance Simulation of a High Speed ADC-Based TOF-PET Read-Out System
2012 / IEEE
By: Rohrich, D.; Brekke, N.; Gruner, R.; Ullaland, K.;
Texture-adaptive skin detection for TV and its real-time implementation on DSP and FPGA
2012 / IEEE
By: Zafarifar, B.; de With, P.H.N.; van den Kerkhof, T.;
Development of an embedded module using FPGA technology and Fuzzy technique
2011 / IEEE
By: Cambraia Leite, L.; Batista, E.A.; Basmage Pinheiro Machado, L.; Palmiro, F.;
DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing
2012 / IEEE
By: Sankaralingam, K.; Satish, N.; Chhugani, J.; Nowatzki, T.; Chen-Han Ho; Govindaraju, V.; Changkyu Kim;
Optimizing Hardware Design by Composing Utility-Directed Transformations
2012 / IEEE
By: Constantinides, G.A.; Luk, W.; Todman, T.; Qiang Liu;
ANLS: Adaptive Non-Linear Sampling Method for Accurate Flow Size Measurement
2012 / IEEE
By: Yan Chen; Yu Cheng; Jia Tian; Sheng Wang; Bin Liu; Chengchen Hu;
An adaptive bilateral motion estimation algorithm and its hardware architecture
2012 / IEEE
By: Erbagci, B.; Ozcan, Z.; Cetin, M.; Akin, A.; Hamzaoglu, I.;
Analysis and design of coding and interleaving in a MIMO-OFDM communication system
2012 / IEEE
By: Iqbal, Z.; Heung-No Lee; Nooshabadi, S.;
Closed-Loop Digital Predistortion System With Fast Real-Time Adaptation Applied to a Handset WCDMA PA Module
2012 / IEEE
By: Presti, C.D.; Asbeck, P.M.; Kimball, D.F.;
Implementation of QRD-RLS algorithm on FPGA. Application to Noise Canceller System
2011 / IEEE
By: Martinez, M.E.I.;
FPGA-based simultaneous multichannel fm broadcast receiver for audio indexing applications in consumer electronics scenarios
2012 / IEEE
By: Tietche, B.H.; Romain, O.; Denby, B.; Dieuleveult, F.D.;
A spherical multi-camera system with real-time omnidirectional video acquisition capability
2012 / IEEE
By: Tasci, T.; Popovic, V.; Afshari, H.; Leblebici, Y.; Schmid, A.;
ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules
2012 / IEEE
By: Wai-Kei Mak; Shao-Huan Wang; Tien-Yu Kuo; Yu-Yi Liang;
An FPGA-Based Hardware Implementation of Configurable Pixel-Level Color Image Fusion
2012 / IEEE
By: Fragoulis, N.; Tsagaris, V.; Besiris, D.; Theoharatos, C.;
synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs
2012 / IEEE
By: Patel, H.D.; Sinha, R.;
Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010
2012 / IEEE
By: Anderson, J.H.; Gort, M.;
Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays
2012 / IEEE
By: Pozzi, L.; Tanimura, K.; Ansaloni, G.; Dutt, N.;
Bandwidth-Sensitivity-Aware Arbitration for FPGAs
2012 / IEEE
By: Stitt, G.; Lu Hao;
Comparison of Preemption Schemes for Partially Reconfigurable FPGAs
2012 / IEEE
By: Edahiro, M.; Tomiyama, H.; Jozwik, K.; Takada, H.; Honda, S.;
A Subspace-Based Two-Way Ranging System Using a Chirp Spread Spectrum Modem, Robust to Frequency Offset
2012 / IEEE
By: Jong-Wha Chong; Myungkyun Kwak; Daegun Oh;
Efficient Optical Pattern Detection for Microcavity Sensors Based Lab-on-a-Chip
2012 / IEEE
By: Sawan, M.; Zonghua Gu; Guoxing Wang; Zhongduo Lin; Guoguang Rong; Yongxin Zhu; Yingjie Cao;
Frequency Estimation Using a Genetic Algorithm With Regularization Implemented in FPGAs
2012 / IEEE
By: Simoes, E.V.; Oleskovicz, M.; de Carvalho, J.R.; Delbem, A.C.B.; Coury, D.V.; da Silva, T.V.; Barbosa, D.;
FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging
2012 / IEEE
By: Hai Li; Alqasemi, U.; Quing Zhu; Aguirre, A.;
A multifunctional, reconfigurable pulse generator for high-frequency ultrasound imaging
2012 / IEEE
By: Weibao Qiu; Lei Sun; Fu Keung Tsang; Yanyan Yu;
System-on-chip design for ultrasonic target detection using split-spectrum processing and neural networks
2012 / IEEE
By: Sungjoon Yoon; Oruklu, E.; Saniie, J.;
A Real-Time QKD System Based on FPGA
2012 / IEEE
By: Kai Chen; Teng-Yun Chen; Hao Liang; Lei Zhou; Sheng-Zhao Lin; Jian-Wei Pan; Ke Cui; Jian Wang; Hong-Fei Zhang; Chun-Li Luo;
Ultrasonic scanner for in vivo measurement of cancellous bone properties from backscattered data
2012 / IEEE
By: Tymkiewicz, R.; Lewandowski, M.; Cieslik, L.; Litniewski, J.; Nowicki, A.; Zienkiewicz, B.;
Look-Up Table Implementation of a Slow Envelope Dependent Digital Predistorter for Envelope Tracking Power Amplifiers
2012 / IEEE
By: Montoro, G.; Gilabert, P.L.;
Quantifying Intrinsic Parallelism Using Linear Algebra for Algorithm/Architecture Coexploration
2012 / IEEE
By: Tsung-Yuan Huang; Chun-Fu Chen; He-Yuan Lin; Gwo Giun Lee;
Testing Ourselves
2012 / IEEE
By: Sevgi, L.;
FPGA Implementation of BASK-BFSK-BPSK Digital Modulators [Testing Ourselves]
2012 / IEEE
By: Erdogan, C.; Minaei, S.; Myderrizi, I.;
A Hybrid Architecture for Compressive Sensing 3-D CT Reconstruction
2012 / IEEE
By: Jianwen Chen; Yi Zou; Yan, M.; Villasenor, J.; Vese, L.A.; Cong, J.;
Hardware-Assisted Detection of Malicious Software in Embedded Systems
2012 / IEEE
By: Rahmatian, M.; Bozorgzadeh, E.; Harris, I.G.; Kooti, H.;
A Novel Architecture for Hyperspectral Endmember Extraction by Means of the Modified Vertex Component Analysis (MVCA) Algorithm
2012 / IEEE
By: Sarmiento, R.; Lopez, J.F.; Callico, G.M.; Horstrand, P.; Lopez, S.;
Software-Defined Sphere Decoding for FPGA-Based MIMO Detection
2012 / IEEE
By: McAllister, J.; Xuezheng Chu;
A Multistandard Digital HD/SD Audio Multiplexer With Modular Ancillary Packet Substitution
2012 / IEEE
By: Graziano, M.; Scavarda, M.; Franchino, D.; Crepaldi, M.;
A Universal Adaptive Driving Scheme for Synchronous Rectification in LLC Resonant Converters
2012 / IEEE
By: Daocheng Huang; Mattavelli, P.; Lee, F.C.; Weiyi Feng;
Ultrasound array transmitter architecture with high timing resolution using embedded phase-locked loops
2012 / IEEE
By: Freear, S.; Ky, C.V.; Raiton, B.; Cowell, D.M.J.; Smith, P.R.;
Experimental Evaluation of Voltage Positive Feedback Based Anti-Islanding Algorithm: Multi-Inverter Case
2012 / IEEE
By: Agbossou, K.; Cardenas, A.;
Decentralized Fault Diagnosis and Its Hardware Implementation for Distribution Substations
2012 / IEEE
By: Wen-Hui Chen;
Parallel Searching-Based Sphere Detector for MIMO Downlink OFDM Systems
2012 / IEEE
By: Radosavljevic, P.; Cavallaro, J.R.; Hao Shen; Kyeong Jin Kim;
Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory
2012 / IEEE
By: Ullah, Z.; Sanghyeon Baeg; Kim Ilgon;
Multiplication by Rational Constants
2012 / IEEE
By: de Dinechin, F.;
A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform
2012 / IEEE
By: Chengjun Zhang; Ahmad, M.O.; Chunyan Wang;
Biologically Inspired Spiking Neurons: Piecewise Linear Models and Digital Implementation
2012 / IEEE
By: Ahmadi, A.; Soleimani, H.; Bavandpour, M.;
Efficient Bi-Directional Digital Communication Scheme for Isolated Switch Mode Power Converters
2012 / IEEE
By: Rinne, K.; Scanlan, A.; Halton, M.; Scharrer, M.;
Fuzzy Hardware: A Retrospective and Analysis
2012 / IEEE
By: Zavala, A.H.; Nieto, O.C.;
Real-Time Architecture for a Robust Multi-Scale Stereo Engine on FPGA
2012 / IEEE
By: Diaz, J.; Barranco, F.; Vanegas, M.; Tomasi, M.; Ros, E.;
Scalable Packet Classification on FPGA
2012 / IEEE
By: Prasanna, V.K.; Weirong Jiang;
An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs
2012 / IEEE
By: Jones, P.H.; Monga, M.; Song Sun; Zambreno, J.;
VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter
2012 / IEEE
By: Darwazeh, I.; Isam, S.; Perrett, M.R.; Whatmough, P.N.;
A Large 3D Swept-Volume Video Display
2012 / IEEE
By: Gately, M.B.; Tull, M.P.; Sawalha, L.; Barnes, R.D.; Yeary, M.; Sluss, J.J.;
Towards to SHA-3 Hashing Standard for Secure Communications: On the Hardware Evaluation Development
2012 / IEEE
By: Sklavos, N.;
Architectural Characterization and Code Compression in Embedded Processors
2012 / IEEE
By: Dias, W.R.A.; da S Barreto, R.; Moreno, E.D.;
The reliability and availability analysis of SEU mitigation techniques in SRAM-based FPGAs
2009 / IEEE / 978-1-4577-0493-2
By: Hong-Xia Guo; Zhi-Bin Yao; Li-Li Ding; Zhong-Ming Wang; Min Lv; Hui Zhou;
Chain coding streamed images through crack run-length encoding
2010 / IEEE / 978-1-4244-9631-0
By: Bailey, D.G.;
Performance study of spike visual processing on a Supercomputer: AER-based spike convolution processing on a 320-core cluster
2011 / IEEE / 978-1-4577-0139-9
By: Morgado-Estevez, A.; Perez-Pena, F.; Montero-Gonzalez, R.; Jimenez, G.; Rodriguez, M.A.; Linares-Barranco, A.; Paz, R.;
An efficient CORDIC arithmetic unit for 3-phase voltage grid synchronization
2011 / IEEE / 978-1-4244-9312-8
By: Garcera, G.; Figueres, E.; Gonzalez-Espin, F.; Patrao, I.;
Architectural design tool for low area band matrix LU factorization
2011 / IEEE / 978-1-61284-466-4
By: Oruklu, E.; Aslan, S.; Saniie, J.;
A study on fine granular fault tolerance methodologies for FPGAs
2011 / IEEE / 978-1-4577-0642-4
By: Niknahad, M.; Becker, J.; Sander, O.;
Model-based software-defined radio(SDR) design using FPGA
2011 / IEEE / 978-1-61284-466-4
By: In Soo Ahn; Mensinger, M.C.; Rodriguez, A.S.; Yufeng Lu;
New developments at CAFADIS plenoptic camera
2011 / IEEE / 978-1-4577-1226-5
By: Montilla, I.; Femenia, B.; Rodriguez-Ramos, L.F.; Militello, C.; Quintero, H.; Guadalupe, V.; Rosa, F.; Lopez, R.; Sanluis, J.C.; Dominguez-Conde, C.; Fernandez-Valdivia, J.J.; Lopez, M.; Puga, M.; Trujillo-Sevilla, J.; Luke, J.P.; Marichal-Hernandez, J.G.; Rodriguez-Ramos, J.M.;
Design of data collection and transmission system based on AD7865
2011 / IEEE / 978-1-61284-774-0
By: Zhi Zhong; Yun-fei Guan;
Low-cost real-time stereo vision hardware with binary confidence metric and disparity refinement
2011 / IEEE / 978-1-61284-774-0
By: Claesen, L.; Motten, A.;
Spacewire codec module analysis
2011 / IEEE / 978-1-61284-774-0
By: Huazhang Zhou; Weigong Zhang; Shuran Di; Feng Ba;
Multi-rate QC-LDPC scheme for narrowband powerline communication system
2011 / IEEE / 978-1-4244-9538-2
By: Fang Yang; Qi Zhang; Jian Song;
Performance evaluation of a Turbo Codec with Log-MAP algorithm on FPGA and CPU
2011 / IEEE / 978-1-61284-466-4
By: Kaabouch, N.; Moncayo, H.I.R.; Anlei Wang; Wen-Chen Hu;
FPGA glitch power analysis and reduction
2011 / IEEE / 978-1-61284-660-6
By: Shum, W.; Anderson, J.H.;
Distributed Arithmetic for FIR Filter implementation on FPGA
2011 / IEEE / 978-1-61284-774-0
By: Pingzheng Shi; Yajun Zhou;
The design and realization of multi-channel parallel testing system based on FPGA
2011 / IEEE / 978-1-4244-9439-2
By: Yulong Hou; Lina Yu; Yanlu Zheng; Wei Liu; Huixin Zhang;
The design of flight control system for small UAV with static stability
2011 / IEEE / 978-1-4244-9439-2
By: Hongxi Yang; Qingbo Geng;
Design and implementation of the vehicle slide angle estimator based on FPGA
2011 / IEEE / 978-988-17255-9-2
By: Xie Xiaohua; Jia Zengben; Liu Tong; Lian Xi;
Active disturbance rejection approach with application to precision motion control
2011 / IEEE / 978-988-17255-9-2
By: Wu Dan; Chen Ken;
Design of airport video aided surveillance system based on DSP+FPGA
2011 / IEEE / 978-988-17255-9-2
By: Zheng Zhi-Hui; Wang Bo; Liu Xi-Ling;
Morris-Lecar model neurons and neural networks: FPGA implementation and analysis
2011 / IEEE / 978-988-17255-9-2
By: Wei Xi-Le; Wang Jiang; Yang Kang-Le; Deng Bin;
Hybrid modeling of non-stationary process variations
2011 / IEEE / 978-1-4503-0636-2
By: Koushanfar, F.; Majzoobi, M.; Dyer, E.;
Device for video recording and analysis of galloping processes
2011 / IEEE / 978-1-61284-795-5
By: Bykovskiy, F.A.; Samsonov, A.N.;
Fast double-parallel image processing based on FPGA
2011 / IEEE / 978-1-4577-0577-9
By: Ye Li; Wencong Xu; Bin Tian; Qingming Yao;
HeMPS-S: A homogeneous NoC-based MPSoCs framework prototyped in FPGAs
2011 / IEEE / 978-1-4577-0642-4
By: Biazi, A.; Wachter, E.W.; Moraes, F.G.;
Dataflow programming model for reconfigurable computing
2011 / IEEE / 978-1-4577-0642-4
By: Khiar, A.; Gantel, L.; Kessal, L.; Lemonnier, F.; Benkhelifa, A.; Miramond, B.;
A reconfigurable fabric supporting full C/C++ input
2011 / IEEE / 978-1-4577-0642-4
By: Portal, J.V.; Itturriet, F.P.; Rutzig, M.B.; Junqueira, A.A.; Carro, L.;
Towards a Quaternion Complex Logarithmic Number System
2011 / IEEE / 978-1-4244-9457-6
By: Cowles, J.; Arnold, M.G.; Kouretas, I.; Paliouras, V.;
A model-based methodology of programming cyber-physical systems
2011 / IEEE / 978-1-4244-9538-2
By: Kodosky, J.; Hayles, T.; Chandhoke, S.; Guoqiang Wang;
Temperature-based covert channel in FPGA systems
2011 / IEEE / 978-1-4577-0642-4
By: Kepa, K.; Nikodem, M.; Iakymchuk, T.;
Accelerating Computations on FPGA Carry Chains by Operand Compaction
2011 / IEEE / 978-1-4244-9457-6
By: Preusser, T.B.; Spallek, R.G.; Zabel, M.;
A high speed robot vision system with GigE vision extension
2011 / IEEE / 978-1-4244-8115-6
By: Kui Yuan; Wenhao He; Zhengdong Xu; Han Xiao;
Improving Scheduling Techniques in Heterogeneous Systems with Dynamic, On-Line Optimisations
2011 / IEEE / 978-1-61284-709-2
By: Bogdanski, M.; Xin Yao; Becker, T.; Lewis, P.R.;

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