Your Search Results

Use materials about this topic in your textbook!

AcademicPub holds over eight million pieces of educational content - such as case studies and journal articles - for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!
Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

Topic: Flash Memory Cells

Results

Effect of Asymmetric Channel on Charging Behavior of 22-nm Quantum-Dot Floating-Gate Flash Memory Cell
2012 / IEEE
By: Gautam, R.; Shrirao, A.; Patrikar, R. M.;
Study of the charge leakage of dual layer Pt metal nanocrystal-based high-�/SiO2 flash memory cell - a relaxation current point of view
2011 / IEEE / 978-1-4577-0158-0
By: Chen, Y.N.; Mahapatra, S.; Singh, P.K.; Lwin, Z.Z.; Goh, K.E.J.; Pey, K.L.;
A novel flash memory cell and design optimization for high density and low power application
2011 / IEEE / 978-1-4577-1997-4
By: Huiwei Wu; Ru Huang; Qianqian Huang; Zhan Zhan; Poren Tang; Yimao Cai; Shiqiang Qin;
Instruction and Data NAND Flash Memory System for Embedded Systems
2012 / IEEE / 978-1-4673-1401-5
By: Cheong-Ghil Kim; Jung-Hoon Lee;
Flash Memory for Ubiquitous Hardware Security Functions: True Random Number Generation and Device Fingerprints
2012 / IEEE / 978-1-4673-1244-8
By: Suh, G.E.; Malysa, G.; Shuo Wu; Wing-kei Yu; Yinglei Wang; Kan, E.C.;
Investigation of Abnormal $V_{\rm TH}/V_{\rm FB}$ Shifts Under Operating Conditions in Flash Memory Cells With $ \hbox{Al}_{2}\hbox{O}_{3}$ High-
2012 / IEEE
By: Van den Bosch, G.; Jian Fu Zhang; Wei Dong Zhang; Baojun Tang; Van Houdt, J.; Govoreanu, B.; Toledano-Luque, M.;
Performance Coding: Codes for Fast Write and Read in Multi-Level NVMs
2015 / IEEE
By: Cassuto, Y.; Hemo, E.;
Classification Codes for Soft Information Generation from Hard Flash Reads
2014 / IEEE
By: Khayat, Patrick R.; Kaynak, Mustafa N.; Parthasarathy, Sivagnanam;
Advanced 300mm 0.13μm BCD technology from 5V to 80V with highly reliable embedded Flash
2014 / IEEE
By: Iwamoto, K.; Kori, M.; Mifuji, M.; Izumi, N.; Shukuri, S.; Shimizu, S.; Wada, K.; Tanaka, B.; Hamanaka, C.; Uehara, H.; Terada, C.; Doguchi, T.; Mihara, M.; Kasa, Y.; Ukai, K.; Ujiie, Y.;
Degradations due to hole trapping in flash memory cells
1989 / IEEE
By: Swaminathan, B.; Chang, C.; Haddad, S.; Lien, J.;
An investigation of erase-mode dependent hole trapping in flash EEPROM memory cell
1990 / IEEE
By: Van Buskirk, M.; Montalvo, T.; Lien, J.; Bustillo, J.; Wang, A.; Chang, C.; Haddad, S.;
Drain-avalanche induced hole injection and generation of interface traps in thin oxide MOS devices
1990 / IEEE
By: Haddad, S.; Rakkhit, R.; Yue, J.; Chang, C.;
Reliability issues of flash memory cells
1993 / IEEE
By: Masuoka, F.; Endoh, T.; Hemink, G.; Shirota, R.; Aritome, S.;
A symmetrical side wall (SSW)-DSA cell for a 64 Mbit flash memory
1991 / IEEE / 0-7803-0243-5
By: Hokari, Y.; Okazawa, T.; Saitoh, K.; Shirai, H.; Oyama, K.; Kodama, N.;
A reliable bi-polarity write/erase technology in flash EEPROMs
1990 / IEEE
By: Kirisawa, R.; Shirota, R.; Aritome, S.; Masuoka, F.; Sakui, K.; Nakayama, R.; Endoh, T.;
A novel memory cell using flash array contactless EPROM (FACE) technology
1990 / IEEE
By: Park, C.; Fazio, A.; Ong, T.C.; Woo, B.J.; Atwood, G.; Lai, S.; Tam, S.; Holler, M.;
Flash memory goes mainstream
1993 / IEEE
By: Dipert, B.; Hebert, L.;
Successive charging/discharging of gate oxides in SOI MOSFET's by sequential hot-electron stressing of front/back channel
1993 / IEEE
By: Ioannou, D.E.; Zaleski, A.; Hughes, H.L.; Campisi, G.J.;
Flash memory-magnetic disk replacement?
1993 / IEEE
By: Barre, A.G.;
New buried channel FLASH memory cell with symmetrical source/drain structure for 64 Mbit or beyond
1994 / IEEE / 0-7803-1921-4
By: Tsubouchi, N.; Inuishi, M.; Ueno, S.; Oda, H.;
New operation mode for stacked-gate flash memory cell
1995 / IEEE
By: Gotou, H.;
Investigation of the soft-write mechanism in source-side injection flash EEPROM devices
1995 / IEEE
By: Wellekens, D.; Van Houdt, J.F.; Maes, H.E.; Groeseneken, G.;
New erase scheme for DINOR flash memory enhancing erase/write cycling endurance characteristics
1994 / IEEE / 0-7803-2111-1
By: Hatanaka, M.; Kunori, Y.; Yuzuriha, K.; Ajika, N.; Tsuji, N.; Miyoshi, H.;
Low-level gate current injections in flash memories initiated by minority carrier collection action of floating terminals
1995 / IEEE
By: Middendorf, M.; Kaya, C.; Huber, B.; Tamer San, K.; Mehrad, F.;
High reliability electron-ejection method for high density flash memories
1995 / IEEE
By: Kawahara, T.; Kimura, K.; Kato, M.; Jyouno, Y.; Saeki, S.; Miyamoto, N.;
Bit-line clamped sensing multiplex and accurate high-voltage generator for 0.25 /spl mu/m flash memories
1996 / IEEE / 0-7803-3136-2
By: Kobayashi, T.; Kawahara, T.; Kimura, K.; Kume, H.; Yugami, J.; Jyouno, Y.; Sato, A.; Kato, M.; Adachi, T.; Miyamoto, N.; Saeki, S.;
A novel Dual String NOR (DuSNOR) memory cell technology scalable to the 256 Mbit and 1 Mbit flash memories
1995 / IEEE / 0-7803-2700-4
By: Park, K.T.; Nam, B.Y.; Kim, M.K.; Choi, Y.B.; Ahn, S.T.; Kim, J.Y.; Kim, K.S.; Yoo, J.W.; Kwon, O.H.;
Multi-level flash/EPROM memories: new self-convergent programming methods for low-voltage applications
1995 / IEEE / 0-7803-2700-4
By: Min-Hwa Chi; Bergemont, A.;
Short channel enhanced degradation during discharge of flash EEPROM memory cell
1995 / IEEE / 0-7803-2700-4
By: Shengwen Luan; Hsu, J.; Jian Chen; Jih Lien; Yuan Tang; Longcor, S.; Chi Chang; Haddad, S.; Liu, D.;
Programming and erase with floating-body for high density low voltage flash EEPROM fabricated on SOI wafers
1995 / IEEE / 0-7803-2547-8
By: Min-Hwa Chi; Bergemont, A.;
Low voltage NVG/sup TM/: a new high performance 3 V/5 V flash technology for portable computing and telecommunications applications
1996 / IEEE
By: Min-Hwa Chi; Bergemont, A.; Haggag, H.;
A multilevel-cell 32 Mb flash memory
1995 / IEEE / 0-7803-2495-1
By: Bauer, M.; Alexis, R.; Wojciechowski, K.; Talreja, S.; Sweha, S.; Rozman, R.; Ruby, P.; Mills, D.; Loe, K.; Leak, D.; Landgraf, M.; Javanifard, J.; Ishac, M.; Hensel, M.; Frary, K.; Fazio, A.; Baltar, B.; Atwood, G.;
A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies
1996 / IEEE
By: Satoh, T.; Hirota, Y.; Yamada, H.; Miwa, T.; Hara, H.;
New interconnect plasma induced damage analyzed by flash memory cell array
1996 / IEEE / 0-7803-3393-4
By: Isobe, K.; Nishimura, T.; Yamada, K.; Takebuchi, M.; Yoshikawa, K.; Uemura, T.; Kimitsuka, A.; Mori, S.; Arakawa, M.; Fujimoto, T.;
Improved performance and reliability of split gate source-side injected flash memory cells
1996 / IEEE / 0-7803-3393-4
By: Liming Hwang; Sharma, U.; Chan, P.; Worley, E.; Li, G.P.; Fox, K.; Lai, K.; Bhattacharya, S.;
Corner-rounded shallow trench isolation technology to reduce the stress-induced tunnel oxide leakage current for highly reliable flash memories
1996 / IEEE / 0-7803-3393-4
By: Aritome, S.; Takeuchi, Y.; Shimizu, K.; Watanabe, H.;
Quick address detection of anomalous memory cells in a flash memory test structure
1997 / IEEE
By: Sakui, K.; Yaegashi, T.; Hazama, H.; Himeno, T.; Miyamoto, J.; Itoh, Y.; Kanda, K.;
Characterization of bitline stress effects on flash cell after program/erase cycle
1997 / IEEE / 0-7803-3575-9
By: Shone, F.; Chang, A.; Wang, M.T.; Huang, C.I.; Chang, K.L.; Guo, J.C.; Liu, V.C.;
A new technique and a test structure for evaluating Vth distribution of flash memory cells
1997 / IEEE / 0-7803-3243-1
By: Sato, S.-I.; Hakozaki, K.; Sakiyama, K.; Iguchi, K.;
Study Of Plasma Charging And Photoresist Coating Effects Using UV-erased FLASH Cell As Charging Sensor
1997 / IEEE / 0-9651-5771-7
By: Maugain, F.; Ghio, E.; Colognese, A.; Alba, S.; Rivera, G.;
A new single-poly flash memory cell with low-voltage and low-power operations for embedded applications
1997 / IEEE / 0-7803-3911-8
By: Min-Hwa Chi; Bergemont, A.;
Simulation of a new EEPROM flash memory cell for high density applications
1997 / IEEE / 0-7803-3790-5
By: Sabesan, L.; Amaratunga, G.A.J.;
Metal etcher characterization using flash memory cells as charge sensors
1997 / IEEE
By: Ghio, E.; Colognese, A.; Alba, S.;
Flash memory cells-an overview
1997 / IEEE
By: Olivo, P.; Bez, R.; Pavan, P.; Zanoni, E.;
Design of a SOI memory cell
1997 / IEEE / 0-7803-3664-X
By: Ioannou, D.E.; Stanojevic, Z.; Osmokrovic, P.; Loncar, B.;
A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using a NAND flash memory technology
1997 / IEEE
By: Ali, S.B.; Hyung-Kyu Lim; Haq, E.; Woung-Moo Lee; Sung-Bu Jun; Heung-Kwun Oh; Myung-Sik Yong; Jong-Chang Son; Kang-Deog Suh; Dong-Gi Lee; San-Hong Kim; Jin-Sun Yum; Byung-Soon Choi; Seung-Keun Lee; Myong-Jae Kim; Sung-Hee Cho; Do-Chan Choi; Tae-Sung Jung;
A 0.24-/spl mu/m/sup 2/ cell process with 0.18-/spl mu/m width isolation and 3-D interpoly dielectric films for 1-Gb flash memories
1997 / IEEE / 0-7803-4100-7
By: Miura, A.; Kurata, H.; Katayama, A.; Sato, A.; Mastsuzaki, N.; Kobayashi, T.; Mine, T.; Kure, T.; Kimura, K.; Kume, H.; Morimoto, T.; Goto, Y.;
Secondary Electron flash-a high performance, low power flash technology for 0.35 /spl mu/m and below
1997 / IEEE / 0-7803-4100-7
By: Gregor, R.W.; Singh, R.; Pinto, M.R.; Mastrapasqua, M.; Bude, J.D.; Kelley, P.J.; Roy, P.K.; McPartland, R.J.; Ma, Y.; Leung, C.W.; Kohler, R.A.;
A triple polysilicon stacked flash memory cell with wordline self-boosting programming
1997 / IEEE / 0-7803-4100-7
By: Chul Ho Shin; Hong Soo Kim; Seong Soon Cho; Dong Jun Kim; Dong Gi Lee; Jung Dal Choi; Sung Tae Ahn;
Novel self-convergent programming scheme for multi-level p-channel flash memory
1997 / IEEE / 0-7803-4100-7
By: Yen-Sen Wang; Ching-Song Yang; Shih-Jye Shen; Wang, A.C.; Rodjy, N.; Chang, S.-D.T.; Hsu, C.C.-H.;
Performance and reliability evaluations of p-channel flash memories with different programming schemes
1997 / IEEE / 0-7803-4100-7
By: Chung, S.S.; Chao, T.S.; Yih, C.M.; Kuo, S.N.;
Stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics
1998 / IEEE
By: Hemink, G.; Satoh, S.; Aritome, S.; Hatakeyama, K.;
Measurement system for a preliminary characterisation of flash memory cells for multilevel applications
1998 / IEEE / 0-7803-4797-8
By: Landi, C.; Faccio, M.; Bucci, G.; Marotta, G.;
New characterization methodology for flash memory cell using CAST structure
1998 / IEEE / 0-7803-4348-4
By: Shone, F.; Wang, M.T.; Guo, J.C.; Liu, U.C.; Fan, M.;
A new method for extracting the capacitance coupling coefficients of sub-0.5-/spl mu/m flash memory cells in the negative gate bias mode
1998 / IEEE / 0-7803-4348-4
By: Ushiyama, M.; Kume, H.; Haraguchi, K.; Ohkura, M.;
1.5 V operation sector-erasable flash memory with BIpolar Transistor Selected (BITS) P-channel cells
1998 / IEEE / 0-7803-4770-6
By: Ajika, N.; Ohnakado, T.; Miyoshi, H.; Satoh, S.; Hayashi, H.; Sugahara, K.; Kobayashi, K.; Takada, H.;
A low voltage operating flash memory cell with high coupling ratio using horned floating gate with fine HSG
1998 / IEEE / 0-7803-4770-6
By: Yamamoto, I.; Honma, I.; Kawata, M.; Kitamura, T.; Oyama, K.; Nishimoto, S.;
A novel step stack NOR cell for low voltage flash
1998 / IEEE / 0-7803-4770-6
By: Kojima, M.; Hori, A.; Ogura, S.; Kotani, H.; Kato, J.; Yamanaka, M.; Akamatsu, K.; Odanaka, S.;
A three-terminal band-trap-band tunneling model for drain engineering and substrate bias effect on GIDL in MOSFET
1998 / IEEE
By: Wang, M.T.; Chou, M.H.; Liu, Y.-C.; Guo, J.-C.; Shone, F.;
Stacked gate mid-channel injection flash EEPROM cell. I. Programming speed and efficiency versus device structure
1998 / IEEE
By: Kim, D.M.; Kwon, W.H.; Cho, M.K.;
Stacked gate mid-channel injection flash EEPROM cell-Part II: analysis of gate current and modeling of programming characteristics
1998 / IEEE
By: Kim, D.M.; Kwon, W.H.; Cho, M.K.;
A 3.42 /spl mu/m/sup 2/ Flash Memory Cell Technology Conformable to a Sector Erase
1991 / IEEE
By: Kawamoto, Y.; Nishida, T.; Kobayashi, T.; Ushiyama, M.; Ohji, Y.; Saeki, S.; Miyamoto, N.; Adachi, T.; Tanaka, T.; Kume, H.; Seki, K.;
A 32-bit RISC microcontroller with 448K bytes of embedded flash memory
1998 / IEEE / 0-7803-4518-5
By: Gallun, C.; Prinz, E.; Jew, T.; Chrudimsky, D.; Kuo, C.; Swift, C.; Choy, J.; Strauss, T.; Eguchi, R.; Harrington, C.; Choe, H.; Pessoney, S.; Wang, B.;
Correlation between plasma-induced gate oxide damage and charging sensor measurements
1998 / IEEE / 0-9651577-2-5
By: Valentini, G.; Micciche', G.; Ghio, E.; Alba, S.; Batani, D.;
A new and flexible scheme for hot-electron programming of nonvolatile memory cells
1999 / IEEE
By: Esseni, D.; Ricco, B.; Cappelletti, P.; Della Strada, A.;
Measurement system for a preliminary characterization of flash memory cells for multilevel applications
1998 / IEEE
By: Bucci, G.; Marotta, G.; Landi, C.; Faccio, M.;
Low-voltage hot electrons and soft-programming lifetime prediction in nonvolatile memory cells
1999 / IEEE
By: Selmi, L.; Ghetti, A.; Bez, R.;
Detailed observation of small leak current in flash memories with thin tunnel oxides
1999 / IEEE
By: Ujiie, K.; Karashima, T.; Nozoe, A.; Kubota, K.; Kanno, H.; Manabe, Y.; Ajika, N.; Okuyama, K.; Nakashima, M.;
Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory
1999 / IEEE
By: Di-Son Kuo; Hung-Cheng Sung; Chii-Wen Chen; Dun-Nian Yaung; Wang, C.S.; Kuo-Ching Huang; Yean-Kuen Fang; Mong-Song Liang;
Proposed on-chip test structure to quantify trap densities within flash meories
1996 / IEEE / 0-8186-7466-0
By: Swaneck, A.; Verma, V.;
On the cell misalignment for multilevel storage FLASH E/sup 2/PROM
1999 / IEEE / 0-7803-5620-9
By: Hemming, M.; Chih Hsin Wang; Ken Su; Chun-Mai Liu; Kordesch, A.V.; Klinger, P.;
A new self-convergent programming and erase tightening by substrate-hot-electron injection for ETOX cells in triple-well
1999 / IEEE / 0-7803-5620-9
By: Chih-Wei Hung; Chih-Ming Chen; Min-Hwa Chi; Yu-Hsiung Wang;
Novel Bi-directional tunneling program/erase NOR (BiNOR) type flash EEPROM
1999 / IEEE / 0-7803-5620-9
By: Ming-Chi Liaw; Tien-Sheng Chao; Cheng-Jye Liu; Yang, E.C.-S.; Hsu, C.C.-H.;
The dominant mechanisms of hot-hole injection induced SILC and their correlation with disturbs in N-flash memory cells
1999 / IEEE / 0-7803-5620-9
By: Ho, Z.H.; Yih, C.M.; Chung, S.S.; Liang, M.S.; Kuo, D.S.; Lin, C.J.;
A novel high performance and reliability p-type floating gate n-channel flash EEPROM
1999 / IEEE / 4-930813-93-X
By: Chung, S.S.; Liang, M.S.; Kuo, D.S.; Lin, C.J.; Yih, C.M.; Ho, Z.H.; Liaw, S.T.; Wu, S.S.;
Novel bi-directional tunneling NOR (BiNOR) type 3-D flash memory cell
1999 / IEEE / 4-930813-93-X
By: Tien-Sheng Chao; Cheng-Jye Liu; Yang, E.C.-S.; Hsu, C.C.-H.; Ming-Chi Liaw;
A new flash memory management for flash storage system
1999 / IEEE / 0-7695-0368-3
By: Han-Joon Kim; Sang-Goo Lee;
A Spice-compatible flash EEPROM model feasible for transient and program/erase cycling endurance simulation
1999 / IEEE / 0-7803-5410-9
By: Wu, S.S.; Yih, C.-M.; Chung, S.S.; Gary Hong; Chen, H.H.;
The scaling properties of CHISEL and CHE injection efficiency in MOSFETs and flash memory cells
1999 / IEEE / 0-7803-5410-9
By: Esseni, D.; Sangiorgi, E.; Ghetti, A.; Selmi, L.;
A new data retention mechanism after endurance stress on flash memory
2000 / IEEE / 0-7803-5860-0
By: Uchida, H.; Nozoe, A.; Manabe, Y.; Okuyama, K.; Kume, H.; Hidaka, M.; Kamohara, S.; Okuyama, Y.; Kameyama, H.; Kubota, K.; Ogura, K.;
A multilevel-cell 32 Mb flash memory
2000 / IEEE / 0-7695-0692-5
By: Bauer, M.; Alexis, R.; Wojciechowski, K.; Talreja, S.; Sweha, S.; Rozman, R.; Ruby, P.; Mills, D.; Loe, K.; Leak, D.; Landgraf, M.; Javanifard, J.; Ishac, M.; Hensel, M.; Frary, K.; Fazio, A.; Baltar, B.; Atwood, G.;
1.25 volt, low cost, embedded flash memory for low density applications
2000 / IEEE / 0-7803-6309-4
By: McPartland, R.J.; Singh, R.;
A study of electrical characteristics and reliability on flash EEPROM cell
2000 / IEEE / 0-7803-6486-4
By: Jong-Hwa Lee; Yun-Gueon Shin;
Fast voltage regulator for multilevel flash memories
2000 / IEEE / 0-7695-0689-5
By: Torelli, G.; Gregori, S.; Micheloni, R.; Khouri, O.;
An analysis of program and erase operation for FC-SGT flash memory cells
2000 / IEEE / 0-7803-6279-9
By: Sakuraba, H.; Endoh, T.; Hioki, M.; Masuoka, F.; Lenski, M.;
NROM: A novel localized trapping, 2-bit nonvolatile memory cell
2000 / IEEE
By: Bloom, I.; Pavan, P.; Eitan, B.; Finzi, D.; Frommer, A.; Aloni, E.;
Metal etcher characterization using flash memory cells as charge sensors
1998 / IEEE
By: Ghio, E.; Colognese, A.; Alba, S.;
Opposite side floating gate SOI FLASH memory cell
2000 / IEEE / 0-7803-6304-3
By: Mansun Chan; Xinnan Lin; Hongmei Wang;
Data retention failure in NOR flash memory cells
2001 / IEEE / 0-7803-6587-9
By: Young-Min Park; Dong-Kyu Lee; Lee, W.H.; Kang-Deog Suh; Kun-Ok Ahn; Keon-Soo Kim;
New technique for fast characterization of SILC distribution in flash arrays
2001 / IEEE / 0-7803-6587-9
By: Ielmini, D.; Visconti, A.; Confalonieri, L.; Lacaita, A.L.; Spinelli, A.S.;
Demonstration of a flash memory cell with 55 /spl Aring/ EOT silicon nitride tunnel dielectric
2001 / IEEE / 0-7803-6412-0
By: Ma, T.P.; Melik-Martirosian, A.; van Duuren, M.J.; van der Wal, V.J.D.; Wolters, D.R.; Widdershoven, F.P.; Guo, X.; Wang, X.W.;
A programming method for multilevel analog flash memory using coarse and fine sequence
2001 / IEEE / 0-7803-6412-0
By: Chun-Mai Liu; Holzmann, P.; Hemming, M.; Ping Guo; Ken Su; Awsare, S.; Kordesch, A.V.; Brennan, J., Jr.;
Mobile ion-induced data retention failure in NOR flash memory cell
2001 / IEEE
By: Keon-Soo Kim; Dong-Kyu Lee; Lee, W.H.; Kang-Deog Suh; Kun-Ok Ahn;
A new compact DC model of floating gate memory cells without capacitive coupling coefficients
2002 / IEEE
By: Pietri, S.; Pavan, P.; Larcher, L.; Marmiroli, A.; Albani, L.;
An embedded NORST flash memory technology
2001 / IEEE / 0-7803-6520-8
By: Zeng Ying; Liu Kai; Pan Liyang; Zhu Jun; Guo Yinzi;
Low power design of embedded NOR type FLASH memory module (EFMM)
2001 / IEEE / 0-7803-6677-8
By: Seung-Min Lee; Myung-Ok Lee, M.; Young-Cheol Kim; Young-Min Kim;
Radiation effects on floating-gate memory cells
2001 / IEEE
By: Wyss, J.; Chimenton, A.; Pellati, P.; Cellere, G.; Paccagnella, A.; Larcher, L.; Modelli, A.;
Cause of data retention loss in a nitride-based localized trapping storage flash memory cell
2002 / IEEE / 0-7803-7352-9
By: Gu, S.H.; Tsai, W.J.; Chih-Yuan Lu; Pan, S.; Zous, N.K.; Tahui Wang; Chen, C.H.; Liu, C.C.; Yeh, C.C.;
Effects of floating-gate interference on NAND flash memory cell operation
2002 / IEEE
By: Jae-Duk Lee; Jung-Dal Choi; Sung-Hoi Hur;
A self adaptive programming method with 5 mV accuracy for multi-level storage in FLASH
2002 / IEEE / 0-7803-7250-6
By: Chun-Mai Liu; Kordesch, A.V.; Engh, L.D.;

Next Page
Return To Top