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Topic: Finfets

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Comparative Analysis of SEU in FinFET SRAM Cells for Superthreshold and Subthreshold Supply Voltage Operation
2011 / IEEE
By: Rathod, S.S.; Dasgupta, S.; Saxena, A.K.;
Tri-Mode Independent-Gate FinFETs for Dynamic Voltage/Frequency Scalable 6T SRAMs
2011 / IEEE
By: Gupta, S.K.; Roy, K.; Park, S.P.;
Variation Study of the Planar Ground-Plane Bulk MOSFET, SOI FinFET, and Trigate Bulk MOSFET Designs
2011 / IEEE
By: Moroz, V.; Xin Sun; Tsu-Jae King Liu; Changhwan Shin; Damrongplasit, N.;
Asymmetrically Doped FinFETs for Low-Power Robust SRAMs
2011 / IEEE
By: Moradi, F.; Roy, K.; Mahmoodi, H.; Wisland, D.T.; Panagopoulos, G.; Gupta, S.K.;
Laser- and Heavy Ion-Induced Charge Collection in Bulk FinFETs
2011 / IEEE
By: Schrimpf, R.D.; Reed, R.A.; Hooten, N.; Pate, N.D.; Zhang, E.X.; El-Mamouni, F.; Vizkelethy, G.; Linten, D.; Griffoni, A.; Claeys, C.; Simoen, E.; Warner, J.; McMorrow, D.; Galloway, K.F.;
Variability of Inversion-Mode and Junctionless FinFETs due to Line Edge Roughness
2011 / IEEE
By: Leung, G.; Chi On Chui;
Fin Width and Bias Dependence of the Response of Triple-Gate MOSFETs to Total Dose Irradiation
2011 / IEEE
By: Ohyun Kim; Yoon-Ha Jeong; Chan-Hoon Park; Fleetwood, D.M.; Jae-Joon Song; Schrimpf, R.D.; En Xia Zhang; Bo Kyoung Choi;
Comparison of the Low-Frequency Noise of Bulk Triple-Gate FinFETs With and Without Dynamic Threshold Operation
2011 / IEEE
By: Simoen, E.; Martino, J.A.; de Andrade, M.G.C.; Claeys, C.;
Variability Analysis of Scaled Crystal Channel and Poly-Si Channel FinFETs
2012 / IEEE
By: O'uchi, S.; Endo, K.; Matsukawa, T.; Kamei, T.; Yongxun Liu; Masahara, M.; Tsukada, J.; Sakamoto, K.; Ogura, A.; Hayashida, T.; Ishikawa, Y.; Yamauchi, H.;
Fin-Height Effect on Poly-Si/PVD-TiN Stacked-Gate FinFET Performance
2012 / IEEE
By: Migita, S.; Morita, Y.; Matsukawa, T.; Mizubayashi, W.; O'uchi, S.; Liu, Y.; Endo, K.; Hayashida, T.; Masahara, M.; Ogura, A.; Yamauchi, H.; Ishikawa, Y.; Tsukada, J.; Kamei, T.; Kosemura, D.; Hashiguchi, H.; Ota, H.;
Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures
2012 / IEEE
By: Agrawal, M.; Shrivastava, M.; Rao, V.R.; Sharma, D.K.; Schulz, T.; Gossner, H.; Mahajan, S.;
Low-Frequency-Noise Investigation of n-Channel Bulk FinFETs Developed for One-Transistor Memory Cells
2012 / IEEE
By: Claeys, C.; Collaert, N.; Aoulaiche, M.; de Andrade, M.G.C.; Simoen, E.;
Compact Capacitance Model of Undoped or Lightly Doped Ultra-Scaled Triple-Gate FinFETs
2012 / IEEE
By: Dimitriadis, C.A.; Tassis, D.H.; Tsormpatzoglou, A.; Fasarakis, N.; Pappas, I.; Ghibaudo, G.; Bucher, M.; Papathanasiou, K.;
Effectiveness of Stressors in Aggressively Scaled FinFETs
2012 / IEEE
By: Ho, B.; Nuo Xu; Liu, T.-J.K.; Moroz, V.; Munkang Choi;
Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights
2012 / IEEE
By: Chenming Hu; Sachid, A.B.;
Performance Breakthrough in Gate-All-Around Nanowire n- and p-Type MOSFETs Fabricated on Bulk Silicon Substrate
2012 / IEEE
By: Yi Song; Chao Zhao; Qingqing Liang; Jiebin Niu; Huajie Zhou; Jun Luo; Qiuxia Xu;
A Lambert-Function Charge-Based Methodology for Extracting Electrical Parameters of Nanoscale FinFETs
2012 / IEEE
By: Papathanasiou, K.; Tsormpatzoglou, A.; Dimitriadis, C.A.; Ghibaudo, G.; Tassis, D.H.; Fasarakis, N.;
Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs
2012 / IEEE
By: Tsormpatzoglou, A.; Fasarakis, N.; Dimitriadis, C.A.; Ghibaudo, G.; Bucher, M.; Papathanasiou, K.; Pappas, I.; Tassis, D.H.;
Neutron-Induced Charge Collection Simulation of Bulk FinFET SRAMs Compared With Conventional Planar SRAMs
2011 / IEEE
By: Yi-Pin Fang; Oates, A.S.;
Decomposition of On-Current Variability of nMOS FinFETs for Prediction Beyond 20 nm
2012 / IEEE
By: O'uchi, S.; Liu, Y.; Matsukawa, T.; Masahara, M.; Sakamoto, K.; Mizubayashi, W.; Endo, K.; Morita, Y.; Migita, S.; Ota, H.; Ishikawa, Y.; Yamauchi, H.; Tsukada, J.;
Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance Metric, Process Variation, Underlapped FinFET, and Temperature Effect
2011 / IEEE
By: Raj, B.; Dasgupta, S.; Saxena, A.K.;
Heavy-Ion-Induced Current Transients in Bulk and SOI FinFETs
2012 / IEEE
By: Ball, D.R.; Zhang, E.X.; El-Mamouni, F.; Vizkelethy, G.; Simoen, E.; Linten, D.; Sierawski, B.; Fleetwood, D.M.; Alles, M.L.; Reed, R.A.; Schrimpf, R.D.; King, M.P.;
Simulation Analysis of Bipolar Amplification in Independent-Gate FinFET and Multi-Channel NWFET Submitted to Heavy-Ion Irradiation
2012 / IEEE
By: Munteanu, D.; Autran, J.L.;
Soft Error Susceptibilities of 22 nm Tri-Gate Devices
2012 / IEEE
By: Seifert, N.; Gill, B.; Jahinuzzaman, S.; Basile, J.; Ambrose, V.; Quan Shi; Allmon, R.; Bramnik, A.;
Charge Pumping Measurements of Radiation-Induced Interface-Trap Density in Floating-Body SOI FinFETs
2012 / IEEE
By: Schrimpf, R.D.; Francis, S.A.; Zhang, C.X.; Duan, G.X.; Fleetwood, D.M.; Zhang, E.X.;
Device- and Circuit-Level Variability Caused by Line Edge Roughness for Sub-32-nm FinFET Technologies
2012 / IEEE
By: Chi On Chui; Gupta, P.; Liangzhen Lai; Leung, G.;
A Correlative Analysis Between Characteristics of FinFETs and SRAM Performance
2012 / IEEE
By: Yamauchi, H.; Tsukada, J.; Sakamoto, K.; Matsukawa, T.; Masahara, M.; Ishikawa, Y.; O'uchi, S.; Endo, K.; Yongxun Liu;
NBTI in n-Type SOI Access FinFETs in SRAMs and Its Impact on Cell Stability and Performance
2012 / IEEE
By: Roy, K.; Panagopoulos, G.; Gupta, S.K.;
A Gate-Dielectric-Last Process via Photosolidification of Liquid Resin
2012 / IEEE
By: Meyyappan, M.; Yang-Kyu Choi; Jin-Woo Han;
Variability Impact of Random Dopant Fluctuation on Nanoscale Junctionless FinFETs
2012 / IEEE
By: Leung, G.; Chi On Chui;
Device Design Guidelines for Nanoscale FinFETs in RF/Analog Applications
2012 / IEEE
By: Jeong-Soo Lee; Chang Yong Kang; Chang-Woo Sohn; Yoon-Ha Jeong; Lee, J.C.; Rock-Hyun Baek; Chang-Ki Baek; Eui-Young Jeong; Hyun Chul Sagong; Do-Young Choi;
Process-Dependent N/PBTI Characteristics of TiN Gate FinFETs
2012 / IEEE
By: Jin Ju Kim; Byoung Hun Lee; Groeseneken, G.; Horiguchi, N.; Togo, M.; Chiarella, T.; Young Gon Lee; Ukjin Jung; Pantisano, L.; Moonju Cho;
Body-Tied Germanium FinFETs Directly on a Silicon Substrate
2012 / IEEE
By: Cheng-Ting Chung; Che-Wei Chen; Chao-Hsin Chien; Guang-Li Luo;
Testing of Stuck-Open Faults in Nanometer Technologies
2012 / IEEE
By: Segura, J.; Hawkins, C.; Gomez, R.; Barcelo, S.; Hernandez, J.V.; Champac, V.;
Nanoscale RingFETs
2012 / IEEE
By: Gokirmak, A.; Silva, H.; Williams, N.;
Fault Models for Logic Circuits in the Multigate Era
2012 / IEEE
By: Bhoj, A.N.; Jha, N.K.; Simsir, M.O.;
Tuning Source/Drain Extension Profile for Current Matching in Nanowire CMOS Logic
2012 / IEEE
By: Singh, N.; Anand, B.; Dasgupta, S.; Maheshwaram, S.; Manhas, S.K.; Kaushal, G.;
Time-Dependent Dielectric Breakdown on Subnanometer EOT nMOS FinFETs
2012 / IEEE
By: Groeseneken, G.; San Andres, E.; Togo, M.; Toledano-Luque, M.; Kauerauf, T.; Feijoo, P.C.;
A Novel Drain-Extended FinFET Device for High-Voltage High-Speed Applications
2012 / IEEE
By: Gossner, H.; Shrivastava, M.; Rao, V.R.;
High-Performance Poly-Si Thin-Film Transistors With L-Fin Channels
2012 / IEEE
By: Je-Wei Lin; Po-Yi Kuo; Yi-Hsien Lu; Tien-Sheng Chao; Yi-Hsuan Chen; Yi-Hong Wu;
Realizing and and or Functions With Single Vertical-Slit Field-Effect Transistor
2012 / IEEE
By: Pfitzner, A.; Kasprowicz, D.; Dim-Lee Kwong; Lo, G.Q.; Maly, W.; Nansheng Shen; Zhixian Chen; Kamath, A.; Singh, N.;
Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs
2012 / IEEE
By: Ho, B.; Nuo Xu; Tsu-Jae King Liu; Faynot, O.; Andrieu, F.; Poiroux, T.; Weber, O.; Bich-Yen Nguyen; Smith, L.;
Impact of Fin Doping and Gate Stack on FinFET (110) and (100) Electron and Hole Mobilities
2012 / IEEE
By: Tat Ngai; Jammy, R.; Injo Ok; Baykan, M.O.; Young, C.D.; Akarvardar, K.; Kah-Wee Ang; Kirsch, P.D.; Hobbs, C.; Majhi, P.; Gausepohl, S.; Rodgers, M.P.;
Variability Origins of Parasitic Resistance in FinFETs With Silicided Source/Drain
2012 / IEEE
By: Sakamoto, K.; O'uchi, S.; Yamauchi, H.; Ishikawa, Y.; Masahara, M.; Endo, K.; Yongxun Liu; Matsukawa, T.; Tsukada, J.;
Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements
2012 / IEEE
By: Groeseneken, G.; Horiguchi, N.; Togo, M.; Magnone, P.; Franco, J.; Alioto, M.; Crupi, F.;
Modeling of ionizing radiation-induced degradation in multiple gate field effect transistors
2009 / IEEE / 978-1-4577-0493-2
By: Esqueda, I.S.; Schrimpf, R.D.; Mamouni, F.E.; Holbert, K.E.; Barnaby, H.J.;
Total-dose effects caused by high-energy neutrons and �-rays in Multiple-Gate FETs
2009 / IEEE / 978-1-4577-0493-2
By: Kilchytska, V.; Flandre, D.; Berger, G.; Militaru, O.; Rooyakers, R.; Collaert, N.; Alvarado, J.;
Angular and strain dependence of heavy-ions induced degradation in SOI FinFETs
2009 / IEEE / 978-1-4577-0493-2
By: Griffoni, A.; Claeys, C.; Simoen, E.; Paccagnella, A.; Meneghesso, G.; Gerardin, S.;
A novel Kondo effect in single atom transistors
2010 / IEEE / 978-1-4244-5261-3
By: Lansbergen, G.P.; Tettamanzi, G.C.; Rogge, S.; Blaauboer, M.; Biesemans, S.; Collaert, N.; Verduijn, J.;
Characterization and failure analysis of Sub-10 nm diameter, gate-all-around nanowire field-effect transistors subject to electrostatic discharge (ESD)
2011 / IEEE / 978-1-4577-0378-2
By: Jeong, Y.H.; Chung, J.; Lo, G.Q.; Singh, N.; Liou, J.J.; Liu, W.;
Circuit design challenges at the 14nm technology node
2011 / IEEE / 978-1-4503-0636-2
By: Warnock, J.;
High performance N- and P-type gate-all-around nanowire MOSFETs fabricated on bulk Si by CMOS-compatible process
2011 / IEEE / 978-1-61284-244-8
By: Qingqing Liang; Chao Zhao; Jun Luo; Qiuxia Xu; Huajie Zhou; Yi Song;
Advanced FinFET process technology for 20 nm node and beyond
2011 / IEEE / 978-1-4577-0378-2
By: Masahara, M.; Morita, Y.; Ota, H.; O'uchi, S.; Endo, K.; Migita, S.; Mizubayashi, W.; Liu, Y.-X.; Matsukawa, T.;
Novel tellurium co-implantation and segregation for effective source/drain contact resistance reduction and gate work function modulation in n-FinFETs
2011 / IEEE / 978-1-4244-9949-6
By: Kam-Chew Leong; Cheng Guo; Yinjie Ding; Shao-Ming Koh; Yee-Chia Yeo; Samudra, G.S.;
Optimal device design of FinFETs on a bulk substrate
2011 / IEEE / 978-1-4577-0378-2
By: Chia-Long Lin; Hsun Li; Meng-Hsueh Chiang; Wei-Chou Hsu; Yi-Bo Liao; Yu-Shen Lai;
Sub-25nm FinFET with advanced fin formation and short channel effect engineering
2011 / IEEE / 978-1-4244-9949-6
By: Yamashita, T.; Basker, V.S.; Standaert, T.; Yeh, C.-C.; Yamamoto, T.; Maitra, K.; Lin, C.-H.; Faltermeier, J.; Kanakasabapathy, S.; Wang, M.; Sunamura, H.; Jagannathan, H.; Reznicek, A.; Schmitz, S.; Inada, A.; Wang, J.; Adhikari, H.; Berliner, N.; Lee, K.-L.; Kulkarni, P.; Zhu, Y.; Kumar, A.; Bryant, A.; Wu, S.; Kanarsky, T.; Cho, J.; Mclellan, E.; Holmes, S.J.; Johnson, R.C.; Levin, T.; Demarest, J.; Li, J.; Oldiges, P.; Arnold, J.; Colburn, M.; Hane, M.; Mcherron, D.; Paruchuri, V.K.; Doris, B.; Miller, R.J.; Bu, H.; Khare, M.; O'Neill, J.; Leobandung, E.;
Independent double-gate FinFET SRAM technology
2011 / IEEE / 978-1-4577-0378-2
By: Yongxun Liu; Matsukawa, T.; O'uchi, S.; Endo, K.; Masahara, M.;
Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond
2011 / IEEE / 978-1-4244-9949-6
By: Hailing Wang; Leobandung, E.; Oldiges, P.; Haensch, W.; Chung-Hsun Lin; Khare, M.; Williams, R.; Bu, H.; Standaert, T.; Yamashita, T.; Bryant, A.; Guillorn, M.; Chang, J.;
Critical discussion on (100) and (110) orientation dependent transport: nMOS planar and FinFET
2011 / IEEE / 978-1-4244-9949-6
By: Young, C.D.; Baykan, M.O.; Jammy, R.; Datta, S.; Kirsch, P.; Majhi, P.; Thompson, S.; Nishida, T.; Hussain, M.M.; Smith, C.E.; Taylor, W.; Ok, I.; Hobbs, C.; Akarvardar, K.; Madan, H.; Agrawal, A.;
Variability and technology aware SRAM Product yield maximization
2011 / IEEE / 978-1-4244-9949-6
By: Cosemans, S.; Bardon, M.; Miranda, M.; Zuber, P.; Biesemans, S.; Verkest, D.; Roussel, P.; Hoffmann, T.Y.; Mercha, A.; Horiguchi, N.; Chiarella, T.; Dobrovolny, P.;
Low-frequency noise in triple-gate n-channel bulk FinFETs
2011 / IEEE / 978-1-4577-0192-4
By: Collaert, N.; Aoulaiche, M.; Simoen, E.; Claeys, C.;
Assessment of temperature dependence of the low frequency noise in unstrained and strained FinFETs
2011 / IEEE / 978-1-4577-0192-4
By: Simoen, E.; Mercha, A.; Collaert, N.; Carin, R.; Benfdila, A.; Claeys, C.; Cretu, B.; Achour, H.; Talmat, R.; Routoure, J.;
Low-frequency noise in FinFETs with PtSi Schottky-barrier source/drain contacts
2011 / IEEE / 978-1-4577-0192-4
By: Malm, B.G.; Ostling, M.; Olyaei, M.;
Scaling of SOI FinFETs down to fin width of 4 nm for the 10nm technology node
2011 / IEEE / 978-1-4244-9949-6
By: Guillorn, M.; Chang, J.B.; Haensch, W.E.; Ott, J.A.; Solomon, P.M.; Pyzyna, A.; Engelmann, S.U.; Lin, C.-H.;
CACTI-FinFET: An integrated delay and power modeling framework for FinFET-based caches under process variations
2011 / IEEE / 978-1-4503-0636-2
By: Jha, N.K.; Chun-Yi Lee;
On the Potentials of FinFETs for Asynchronous Circuit Design
2011 / IEEE / 978-1-4577-0803-9
By: Mosaffa, M.; Jafari, F.; Mohammadi, S.;
Physics-based modeling of nonplanar nanodevices (FinFETs) and their response to radiation
2011 / IEEE / 978-83-932075-2-7
By: Turowski, M.; Weize Xiong; Raman, A.;
Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration
2011 / IEEE / 978-83-932075-2-7
By: Li, X.; Shen, N.; Chen, Z.; Singh, N.; Maly, W.; Pfitzner, A.; Lin, Y.; Marek-Sadowska, M.; Kuzmicz, W.; Kasprowicz, D.;
Critical analysis of 14nm device options
2011 / IEEE / 978-1-61284-418-3
By: Sathaye, N.; Bajaj, M.; Guo, D.; Xiu, K.; Oldiges, P.; Kulkarni, P.; Muralidhar, R.; Lin, C.;
Nanosized metal grains induced electrical characteristic fluctuation in 16 nm bulk and SOI FinFET devices with TiN/HfO2 gate stack
2011 / IEEE / 978-1-61284-418-3
By: Yiming Li; Hui-Wen Cheng; Hsin-Wen Su; Chun-Yen Yiu;
Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs
2011 / IEEE / 978-1-4577-0223-5
By: Tsuchiya, R.; Takemura, R.; Itoh, K.; Kotabe, A.; Horiguchi, M.;
Variability analysis of scaled poly-Si channel FinFETs and tri-gate flash memories for high density and low cost stacked 3D-memory application
2011 / IEEE / 978-1-4577-0708-7
By: Masahara, M.; Mastukawa, T.; Liu, Y.X.; Ogura, A.; Hayashida, T.; Kamei, T.; Endo, K.; Sakamoto, K.; Ishikawa, Y.; Yamauchi, H.; Tsukada, J.; Oruchi, S.;
On gated diodes for ESD protection in bulk FinFET CMOS technology
2011 / IEEE / 978-1-58537-193-8
By: Griffoni, A.; Thijs, S.; Groeseneken, G.; Hoffmann, T.; Shih-Hung Chen; Linten, D.;
Extracting the conduction band offset in strained FinFETs from subthreshold-current measurements
2011 / IEEE / 978-1-4577-0708-7
By: Schmitz, J.; van Dal, M.J.H.; Esseni, D.; Hueting, R.J.E.; Kemaneci, B.K.; van Hemert, T.;
On the efficiency of stress techniques in gate-last N-type bulk FinFETs
2011 / IEEE / 978-1-4577-0708-7
By: De Keersgieter, A.; Veloso, A.; Collaert, N.; Eneman, G.; Hoffmann, T.Y.; De Meyer, K.;
Comparative study of circuit perspectives for multi-gate structures at sub-10nm node
2011 / IEEE / 978-1-4577-0708-7
By: Boeuf, F.; Ghibaudo, G.; Skotnicki, T.; Coquand, R.; Monfray, S.; Lacord, J.; Huguenin, J.-L.;
Atomic layer deposition of 25-nm-thin sidewall spacer for enhancement of FinFET performance
2011 / IEEE / 978-1-4577-0708-7
By: Yamauchi, H.; Tsukada, J.; Sakamoto, K.; Oruchi, S.; Masahara, M.; Yongxum Liu; Matsukawa, T.; Ishikawa, Y.; Endo, K.;
The future of SOI transistor technology
2011 / IEEE / 978-1-61284-760-3
By: Khakifirooz, A.; Doris, B.; Kangguo Cheng;
FINFET technology a substrate perspective
2011 / IEEE / 978-1-61284-760-3
By: Huiming Bu;
Variability origins of FinFETs and perspective beyond 20nm node
2011 / IEEE / 978-1-61284-760-3
By: Masahara, M.; O'uchi, S.; Endo, K.; Yongxun Liu; Matsukawa, T.;
ESD protection in finfet technologies
2011 / IEEE / 978-1-61284-760-3
By: Thijs, S.;
Competitive SOC with UTBB SOI
2011 / IEEE / 978-1-61284-760-3
By: Skotnicki, T.;
Analysis of parasitic resistance in double gate FinFETs with different fin lengths
2011 / IEEE / 978-1-61284-760-3
By: Yang, X.; Maitra, K.; Miller, R.J.; Bu, H.; Samavedam, S.; Standaert, T.E.; Basker, V.S.; Yamashita, T.; Wang, M.; Kulkarni, P.; Raymond, M.; Zeitzoff, P.; Yeh, C.;
Influence of fin height on poly-Si/PVD-TiN stacked gate FinFET performance
2011 / IEEE / 978-1-61284-760-3
By: Liu, Y.X.; Tsukada, J.; Endo, K.; Hayashida, T.; Masahara, M.; Ogura, A.; Yamauchi, H.; Ishikawa, Y.; O'uchi, S.; Kamei, T.; Kosemura, D.; Hashiguchi, H.; Ota, H.; Morita, Y.; Migita, S.; Mizubayashi, W.; Matsukawa, T.;
Variability analysis and FinFET-based design of XOR and XNOR circuit
2011 / IEEE / 978-1-4577-1386-6
By: Islam, A.; Hasan, M.; Imran, A.;
Impacts of single trap induced random telegraph noise on finfet devices and SRAM cell stability
2011 / IEEE / 978-1-61284-760-3
By: Ching-Te Chuang; Pin Su; Yin-Nien Chen; Hu, V.P.-H.; Ming-Long Fan;
Artificial neural network based modeling of FinFET forward transmission coefficient
2011 / IEEE / 978-1-4577-2019-2
By: Caddemi, A.; Schreurs, D.M.M.-P.; Crupi, G.; Marinkovic, Z.; Markovic, V.;
Gate leakage currents modeling for oxynitride gate dielectric in double gate MOSFETs
2011 / IEEE / 978-1-4577-1013-1
By: Estrada, M.; Cerdeira, A.; Garduno, S.I.;
Modeling of a new liner stressor comprising Ge2Sb2Te5 (GST): Amorphous-crystalline phase change and stress induced in FinFET channel
2011 / IEEE / 978-1-4577-1756-7
By: Ran Cheng; Yee-Chia Yeo; Bin Liu; Yinjie Ding;
A comparative analysis between FinFET Semi-Dynamic Flip-Flop topologies under process variations
2011 / IEEE / 978-1-4673-0465-8
By: Rabie, M.; Anis, M.; Moustafa, E.; Abdelhafez, M.; Bahgat, A.; Nasr, T.; Shobak, H.; Ramadan, K.;
Advanced contact and junction technologies for improved parasitic resistance and short channel immunity in FinFETs beyond 22nm node
2011 / IEEE / 978-1-4577-1756-7
By: Ang, K.-W.; Jammy, R.; Kirsch, P.D.; Hobbs, C.; Gausepohl, S.; Gunji, M.; Franca, D.L.; Rodgers, M.; Ok, I.; Hung, P.Y.; Min, B.-G.;
Analysis of output transconductance of FinFETs incorporating quantum mechanical and temperature effects with 3D temperature distribution
2011 / IEEE / 978-1-4577-1756-7
By: Akanda, M.R.K.; Khosru, Q.D.M.;
Performance investigation of DG-FinFET for subthreshold applications
2011 / IEEE / 978-1-4577-1107-7
By: Hasan, M.; Imran, A.; Pable, S.D.;
Denser and more stable FinFET SRAM using multiple fin heights
2011 / IEEE / 978-1-4577-1756-7
By: Sachid, A.B.; Chenming Hu;
Charge pumping and DCIV currents in SOI FinFETs
2011 / IEEE / 978-1-4577-1756-7
By: Zhang, C.X.; Francis, S.A.; Fleetwood, D.M.; Zhang, E.X.; Schrimpf, R.D.; El-Mamouni, F.;
Comparison of silicon-on-insulator and Body-on-Insulator FinFET based digital circuits with consideration on self-heating effects
2011 / IEEE / 978-1-4577-1756-7
By: Ghosh, P.; Peijie Feng;
Mixed mode simulation of SRAM FinFETS
2012 / IEEE / 978-1-4577-1546-4
By: Nirmal, D.; LakshmiPrabha, V.; Manikandan, M.; Sindhu, P.; Princess Nesamani, I.F.;
Analog parameters of MuGFET devices with different source/drain engineering
2012 / IEEE / 978-1-4577-1117-6
By: Claeys, C.; Aoulaiche, M.; Simoen, E.; Collaert, N.; Martino, J.A.; Rodrigues, M.; Galeti, M.;
Simulation of miller OpAmp analog circuit with FinFET transistors
2012 / IEEE / 978-1-4577-1117-6
By: Pavanello, M.A.; Cerdeira, A.; Contreras, E.;
An analytical estimation model for the spreading resistance of Double-Gate FinFETs
2012 / IEEE / 978-1-4577-1117-6
By: Giacomini, R.; Pereira, A.S.N.; Malheiro, C.T.;

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