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Topic: Dsp Applications

Results

A novel low power, low area array multiplier design for DSP applications
2011 / IEEE / 978-1-61284-653-8
By: Prasad, T.J.; Subbaiah, Y.; Ravi, N.; Rao, T.S.;
A medium-grain reconfigurable processor organization
2011 / IEEE / 978-1-61284-857-0
By: Delgado-Frias, J.G.; Van Dyken, J.;
Alias property propagation and reuse after variable scope change
2011 / IEEE / 978-1-4577-1481-8
By: Burlacu-Zane, A.; Tapus, N.; Nicolescu, A.;
Comparison of reconfigurable FFT processor implementation using CORDIC and multipliers
2011 / IEEE / 978-1-4244-9477-4
By: Bhakthavatchalu, R.; Arya, J.; Abdul Kareem, N.;
Power aware and high speed reconfigurable modified booth multiplier
2011 / IEEE / 978-1-4244-9477-4
By: Sakthi, S.S.; Kayalvizhi, N.;
Dynamic Partial Reconfiguration in FPGAs for DSP Applications
2011 / IEEE / 978-1-4577-1847-2
By: Borkute, C.V.; Kharkar, C.N.; Deshmukh, A.Y.;
Floating-point adaptive CORDIC (FPA-CORDIC) algorithm for elementary function calculation
2011 / IEEE / 978-1-4577-1041-4
By: Gebali, F.;
FFT implementation with Multi-operand floating point units
2011 / IEEE / 978-1-61284-193-9
By: Yuteng Pan; Dongge Wang; Zhang Zhang; Sobelman, G.E.; Xiaofang Zhou; Dan Wang;
A generic, cheap and portable platform for signal processing experiments
2012 / IEEE / 978-1-4673-0342-2
By: Steiger, O.; Grentzinger, B.;
VLSI design methodologies for digital signal processing
1989 / IEEE
By: Tenhunen, H.; Neuvo, Y.; Vainio, O.;
Executing DSP applications in a fine-grained dataflow environment
1991 / IEEE
By: Herath, J.; Radivojevic, I.P.;
On-line arithmetic for DSP applications
1989 / IEEE
By: Ercegovac, M.D.; Lang, T.;
Memory based digital signal processing
1990 / IEEE
By: Mahantshetti, S.S.; Doddington, G.R.; Pawate, B.I.; Smith, D.; Harward, M.G.;
DSP/C: a standard high level language for DSP and numeric processing
1990 / IEEE
By: Leary, K.W.; Waddington, W.;
Open-ended system for high-level synthesis of flexible signal processors
1990 / IEEE / 0-8186-2024-2
By: Van Meerbergen, J.; Pauwels, M.; Goossens, G.; Catthoor, F.; Lanneer, D.; De Man, H.;
Wave digital filters boost DSP applications
1992 / IEEE
By: Lawson, S.;
2-D genetic optimizer algorithm and its application in digital signal processing
1991 / IEEE
By: Chang Yilin; Cheng Weixiong; Li Feipeng;
Improved accuracy for logarithmic addition in DSP applications
1988 / IEEE
By: Bailey, T.; Cowles, J.; Arnold, M.G.;
Formal methods for silicon compilation
1991 / IEEE
By: Kalker, T.;
Models for bit-true simulation and high-level synthesis of DSP applications
1992 / IEEE / 0-8186-2610-0
By: Goossens, G.; Catthoor, F.; Lanneer, D.; Pauwels, M.; De Man, H.;
Basic design techniques for both low-power and high-speed ASICs
1992 / IEEE / 0-8186-2845-6
By: von Kaenol, V.; Piguet, C.; Klootsema, R.; Perotto, J.-F.; Masgonty, J.-M.;
A hardware-software codesign methodology for DSP applications
1993 / IEEE
By: Lee, E.A.; Kalavade, A.;
Throughput optimized architectural synthesis
1993 / IEEE
By: Gebotys, C.H.;
PLS: a scheduler for pipeline synthesis
1993 / IEEE
By: Hsu, Y.-C.; Hwang, C.-T.; Lin, Y.-L.;
Greedy hardware optimization for linear digital circuits using number splitting and refactorization
1993 / IEEE
By: d'Abreu, M.A.; Roy, R.K.; Chatterjee, A.;
The design and implementation of multidimensional systolic arrays for DSP applications
1989 / IEEE
By: Bayoumi, M.A.; Ling, N.;
VLSI architectures for DSP applications: current trends
1992 / IEEE / 0-7803-0510-8
By: Bayoumi, M.A.;
Reconfigurable multi-bit processor for DSP applications in statistical physics
1993 / IEEE / 0-8186-3890-7
By: Monaghan, S.; Cowen, C.P.;
A 13 ns Mb CMOS EPROM using 1-T FAMOS technology
1993 / IEEE / 0-7803-0987-1
By: Payne, J.; Rosendale, G.; Blaha, F.; Allum, D.; Erickson, D.; Larsen, B.; Randazzo, T.; Pathak, S.;
High speed digital filtering on SRAM-based FPGAs
1994 / IEEE / 0-8186-4990-9
By: Ghoshal, S.K.; Nandy, S.K.; Visvanathan, V.; Giri, A.;
The design of a fault tolerant GEQRNS processing element for linear systolic array DSP applications
1994 / IEEE / 0-8186-5610-7
By: Smith, J.C.; Taylor, F.J.;
Comparing the performance of FPGA-based custom computers with general-purpose computers for DSP applications
1994 / IEEE / 0-8186-5490-2
By: Bergmann, N.W.; Mudge, J.C.;
Buffer memory requirements in DSP applications
1994 / IEEE / 0-8186-5885-1
By: Ade, M.; Peperstraete, J.A.; Lauwereins, R.;
A dynamic dataflow model suitable for efficient mixed hardware and software implementations of DSP applications
1994 / IEEE / 0-8186-6315-4
By: Buck, J.T.;
Grape-II: a system-level prototyping environment for DSP applications
1995 / IEEE
By: Lauwereins, R.; Peperstraete, J.A.; Ade, M.; Engels, M.;
The Multimedia Video Processor (MVP): a chip architecture for advanced DSP applications
1994 / IEEE / 0-7803-1948-6
By: Gove, R.J.;
Fast combinatorial RNS processors for DSP applications
1995 / IEEE
By: Orlandi, G.; Piazza, F.; Di Claudio, E.D.;
Technology mapping algorithms for NORA dynamic logic circuits
1993 / IEEE / 0-8186-3410-3
By: Lefebvre, M.C.; Ortiz, R.R.;
A new modulo 2/sup a/+1 multiplier
1993 / IEEE / 0-8186-4230-0
By: Milford, D.; Wrzyszcz, A.;
A novel framework for multi-rate scheduling in DSP applications
1993 / IEEE / 0-8186-3492-8
By: Govindarajan, R.; Gao, G.R.;
RSFQ arithmetic blocks for DSP applications
1995 / IEEE
By: Jao Ching Lin; Polonsky, S.V.; Rylyakov, A.V.;
InSyn: integrated scheduling for DSP applications
1995 / IEEE
By: Sharma, A.; Jain, R.;
A unified scheduling model for high-level synthesis and code generation
1995 / IEEE / 0-8186-7039-8
By: Kifli, A.; De Man, H.; Goossens, G.;
Rate-optimal scheduling for cyclo-static and periodic schedules
1995 / IEEE / 0-7803-2431-5
By: Liang-Fang Chao; Sha, E.H.-M.;
CLIFF: C language interface for the functional simulator
1995 / IEEE / 0-7803-2431-5
By: Baudendistel, K.;
114 MFLOPS logarithmic number system arithmetic unit for DSP applications
1995 / IEEE
By: Lewis, D.M.;
A CMOS gate array architecture for digital signal processing applications
1996 / IEEE
By: Klar, H.; Green, J.-M.;
Designing efficient redundant arithmetic processors for DSP applications
1995 / IEEE / 0-7803-2972-4
By: Paliouras, V.; Stouraitis, T.; Soudris, D.;
Distributed arithmetic-based architectures for high speed IIR filter design
1996 / IEEE / 0-8186-7267-6
By: Yin-Tsung Hwang; Ching-Long Su;
CMOS gate array architecture for digital signal processing applications
1995 / IEEE / 0-7803-2584-2
By: Green, J.-M.; Klar, H.;
Low power filtering using approximate processing for DSP applications
1995 / IEEE / 0-7803-2584-2
By: Chandrakasan, A.; Nawab, S.H.; Ludwig, J.T.;
Design and implementation of a fast and compact residue-based semi-custom VLSI arithmetic chip
1994 / IEEE / 0-7803-2428-5
By: Abdel-Aty-Zohdy, H.S.; Hiasat, A.A.;
114 MFLOPS logarithmic number system arithmetic unit for DSP applications
1995 / IEEE / 0-7803-2495-1
By: Lewis, D.M.;
A hierarchical multiprocessor scheduling system for DSP applications
1995 / IEEE / 0-8186-7370-2
By: Lee, E.A.; Bhattacharyya, S.S.; Pino, J.L.;
Synthesis of domain-specific heterogeneous multiprocessor systems: hybrid video coding schemes
1996 / IEEE / 0-7803-3073-0
By: Thiele, L.; Schobinger, M.;
Synthesis of low area data format converters
1996 / IEEE / 0-7803-3073-0
By: Parhi, K.K.; Majumdar, M.;
Hardware/software co-design for DSP applications via the HMS framework
1996 / IEEE / 0-7803-3192-3
By: Sha, E.H.-M.; Sheliga, M.;
Bit-serial pipeline synthesis for multi-FPGA systems with C++ design capture
1996 / IEEE / 0-8186-7548-9
By: Dai, W.W.-M.; Isshiki, T.;
Multiplication and inner product with field programmable gate arrays
1994 / IEEE / 0-7803-2123-5
By: Ercegovac, M.D.; Louie, M.E.;
Communication-sensitive loop scheduling for DSP applications
1997 / IEEE
By: Passos, N.L.; Sha, E.H.-M.; Tongsima, S.;
Real-time emulation of DSP applications on programmable DSPs and FPGAs
1996 / IEEE / 0-7803-3650-X
By: Lauwereins, R.; Note, S.; Ade, M.;
A reconfigurable processing system for DSP applications
1996 / IEEE / 0-7803-3636-4
By: Knittel, G.;
General-purpose microprocessor performance for DSP applications
1996 / IEEE / 0-8186-7646-9
By: Barkdull, J.N.; Douglas, S.C.;
Programmable DSP systems using FPGA
1996 / IEEE / 0-7803-3679-8
By: Wahab, A.; Tan, E.C.; Wong, K.K.;
Low power, high performance switched-capacitor sigma-delta modulator suitable for battery operated audio signal processing applications
1996 / IEEE / 0-7803-3679-8
By: Ho Yoon San; Hasan, S.M.R.;
High-performance hardware for function generation
1997 / IEEE / 0-8186-7846-1
By: Wei, B.W.Y.; Jun Cao;
A novel VLSI BiCMOS/bipolar concurrent multiplier-accumulator for DSP applications
1993 / IEEE / 0-7803-1316-X
By: Poornaiah, D.V.; Ahmad, M.O.; Ananda Mohan, P.;
Overflow handling in inner-product processors
1997 / IEEE / 0-7803-3905-3
By: Rayhan, A.; Elguibaly, F.;
Constraint analysis for DSP code generation
1997 / IEEE / 0-8186-7949-2
By: Jess, J.A.G.; van Meerbergen, J.L.; Timmer, A.H.; Strik, M.T.J.; Mesman, B.;
An integrated environment for real-time implementation of DSP algorithms
1997 / IEEE / 0-7803-4137-6
By: Livanos, N.-A.I.; Papadimitriou, P.D.; Zigouris, E.;
A constraint driven approach to loop pipelining and register binding
1998 / IEEE / 0-8186-8359-7
By: van Meerbergen, J.L.; Timmer, A.H.; Strik, M.; Mesman, B.; Jess, J.A.G.;
Design of data format converters using two-dimensional register allocation
1998 / IEEE
By: Parhi, K.K.; Majumdar, M.;
APICES-rapid application development with graph pattern
1998 / IEEE / 0-8186-8479-8
By: Bredenfeld, A.;
Reconfigurable hardware for efficient implementation of programmable FIR filters
1998 / IEEE / 0-7803-4428-6
By: Larsson, P.; Nicol, C.J.; Denk, T.C.; Azadet, K.;
Implementation of RNS addition and RNS multiplication into FPGAs
1998 / IEEE / 0-8186-8900-5
By: Maltar, L.; Amorim, C.L.; Alves, V.C.; Franca, M.G.; Felipe, C.B.;
High performance DSPs-what's hot and what's not?
1998 / IEEE / 1-58113-059-7
By: Nicol, C.; Ackland, B.;
A 16-bit parallel MAC architecture for a multimedia RISC processor
1998 / IEEE / 0-7803-4997-0
By: Murata, E.; Kuroda, I.; Okamura, A.; Arai, T.; Suzuki, K.; Nadehara, K.;
MetaCore: an application specific DSP development system
1998 / IEEE / 0-89791-964-5
By: Sang-Jun Nam; In-Hyung Kim; Byoung-Woon Kim; Jin-Hyuk Yang; Chong-Min Kyung; In-Cheol Park; Seung-Ho Hwang; Yong-Hoon Lee; Kyu-Ko Park; Kwang-Il Park; Jun-Sung Kim; Jang-Ho Cho; Chan-Soo Hwang; Kun-Moo Lee; Jae-Yeol Kim; Hyun-Dhong Yoon; Jong-Sun Kim; Jong-Yeol Lee; Dae-Hyun Lee; Young-Su Kwon; Chang-Ho Ryu; Sung-Won Seo;
Code generation for compiled bit-true simulation of DSP applications
1998 / IEEE / 0-8186-8623-5
By: Lauwereins, R.; Ade, M.; De Coster, L.; Peperstraete, J.;
Local memory exploration and optimization in embedded systems
1999 / IEEE
By: Nicolau, A.; Dutt, N.D.; Panda, P.R.;
VHDL modeling and model testing for DSP applications
1999 / IEEE
By: Gray, F.G.; Armstrong, J.R.; Meng-Wei Lin;
General purpose FIR filter arrays using optimized redundancy over direct product polynomial rings
1998 / IEEE / 0-7803-5148-7
By: Miller, W.C.; Li, B.; Muscedere, R.; Jullien, G.A.; Shahkarami, M.;
A novel multirate adaptive FIR filtering algorithm and structure
1999 / IEEE / 0-7803-5041-3
By: Cheng-Shing Wu; An-Yeu Wu;
C/C++ compiler support for Siemens TriCore DSP instruction set
1999 / IEEE / 0-7803-5041-3
By: Hao Shi; Westerholz, K.; Arnold, R.;
Design of low-error fixed-width multipliers for DSP applications
1999 / IEEE
By: Jer Min Jou; Ren Der Chen; Shiann Rong Kuang;
Set theoretic estimation through triangular noise distribution
1999 / IEEE / 0-7803-5471-0
By: Lin, C.Y.; Kuo, C.J.; Deller, J.R., Jr.;
An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications
1999 / IEEE / 1-58113-092-9
By: Kaul, M.; Ouaiss, I.; Govindarajan, S.; Vemuri, R.;
Modeling n/spl times/n bit multiplication blocks for DSP applications using VHDL
1999 / IEEE / 0-7695-0321-7
By: Dervisoglu, A.; Ors, S.B.;
A hardware/software cosimulation environment for DSP applications
1999 / IEEE / 0-7695-0321-7
By: Weiss, R.; Steger, C.; Kreiner, C.;
A new adiabatic technique for designing low power array architectures
1999 / IEEE / 0-7803-5682-9
By: Karafyllidis, I.; Soudris, D.; Lolas, C.Z.; Thanailakis, A.;
Full-custom VLSI design of a new high-speed modular adder structures
1999 / IEEE / 0-7803-5682-9
By: Hiasat, A.A.;
Efficient dataflow representation of MPEG-1 audio (layer III) decoder algorithm with controlled global states
1999 / IEEE / 0-7803-5650-0
By: Chanik Park; Soonhoi Ha; Jaewoong Chung;
A high-speed CORDIC algorithm and architecture for DSP applications
1999 / IEEE / 0-7803-5650-0
By: Kuhlmann, M.; Parhi, K.K.;
FPGA implemented fast two's complement serial-parallel multiplier with PCI interface
1998 / IEEE / 0-7803-4969-5
By: Salama, A.E.; Ashour, M.A.; Khalil, A.H.; Saleh, H.I.;
The evolution of DSP processors
2000 / IEEE
By: Eyre, J.; Bier, J.;
Multi-algorithm ASIP synthesis and power estimation for DSP applications
2000 / IEEE / 0-7803-5482-6
By: Sentieys, O.; Cousin, J.-G.; Chillet, D.;
Design and properties of step-like weighting windows
2000 / IEEE / 0-7803-5482-6
By: Saramaki, T.; Lukin, V.V.;
A new approach to model communication for mapping and scheduling DSP-applications
2000 / IEEE / 0-7803-6293-4
By: Mathis, C.; Weiss, R.; Schneider, R.; Schmid, M.; Rinner, B.;
A scalable loop optimization approach for scalable DSP processors
2000 / IEEE / 0-7803-6293-4
By: Erh-Wen Hu; Bogong Su; Jian Wang;
Contention-conscious transaction ordering in embedded multiprocessors
2000 / IEEE / 0-7695-0716-6
By: Bhattacharyya, S.S.; Khandelia, M.;

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