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Topic: Circuit Layout

Results

TRACAS: An automatic router for circuits designed with the MDMOS symbolism
1985 / IEEE
By: Leblond, A.;
Circuit-Level Layout-Aware Single-Event Sensitive-Area Analysis of 40-nm Bulk CMOS Flip-Flops Using Compact Modeling
2011 / IEEE
By: Massengill, L.W.; Bhuva, B.L.; Sternberg, A.L.; Jagannathan, S.; Kauppila, J.S.; Kauppila, A.V.; Ball, D.R.; Haeffner, T.D.; Loveless, T.D.;
Enhanced Performance in Epitaxial Graphene FETs With Optimized Channel Morphology
2011 / IEEE
By: Gaskill, D.K.; Eddy, C.R.; Myers-Ward, R.L.; Tedesco, J.L.; Yanqing Wu; Dimitrakopoulos, C.; Farmer, D.B.; Yu-Ming Lin; Jenkins, K.A.; Avouris, P.;
Ambiguous Influences Affecting Insertion Loss of Microwave Printed Circuit Boards [Application Notes]
2012 / IEEE
By: Coonrod, J.;
A new approach to designing electronic systems for operation in extreme environments: Part I - The SiGe Remote Sensor Interface
2012 / IEEE
By: Johnson, W.; Holmes, J.; Xueyang Geng; Mantooth, A.; Cornett, K.; Dai, F.; Blalock, B.; Ulaganathan, C.; Garbos, R.; Berger, R.; England, T.D.; Diestelhorst, R.M.; Cressler, J.D.; Eckert, C.; Frampton, R.; Peltz, L.; Mojarradi, M.; McCluskey, P.; Reed, R.; Alles, M.;
A new approach to designing electronic systems for operation in extreme environments: Part II - The SiGe remote electronics unit
2012 / IEEE
By: Barlow, M.; Dai, F.; Blalock, B.; Garbos, R.; Berger, R.; Mantooth, A.; Reed, R.; Alles, M.; Ramachandran, V.; Cressler, J.D.; Kenyon, E.W.; Diestelhorst, R.M.; England, T.D.; Eckert, C.; Frampton, R.; Peltz, L.; Mojarradi, M.; McCluskey, P.; Webber, C.; Holmes, J.; Ellis, C.; Johnson, W.;
Thermal signature: A simple yet accurate thermal index for floorplan optimization
2011 / IEEE / 978-1-4503-0636-2
By: Inhak Han; Jaeha Kung; Youngsoo Shin; Sapatnekar, S.;
Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries
2011 / IEEE / 978-1-4503-0636-2
By: Burns, S.; Ryzhenko, N.;
A distributed algorithm for layout geometry operations
2011 / IEEE / 978-1-4503-0636-2
By: Chiang, C.; Yu-Chuan Pi; Sinha, S.; Kai-Ti Hsu; Tsung-Yi Ho;
3D Thermal-aware floorplanner for many-core single-chip systems
2011 / IEEE / 978-1-4577-1490-0
By: Ayala, J.L.; Risco-Martin, J.L.; Cuesta, D.; Atienza, D.;
A template router
2011 / IEEE / 978-1-4577-0618-9
By: Fernandez, F.V.; Dundar, G.; Unutulmaz, A.;
LDS - A description script for layout templates
2011 / IEEE / 978-1-4577-0618-9
By: Unutulmaz, A.; Dundar, G.; Fernandez, F.V.;
Layout-aware Pareto fronts of electronic circuits
2011 / IEEE / 978-1-4577-0618-9
By: Roca, E.; Castro-Lopez, R.; Toro-Frias, A.; Fernandez, F.V.;
Simulated annealing based thermal-aware floorplanning
2011 / IEEE / 978-1-4577-0321-8
By: Lixia Qi; Lunyao Wang; Yinshui Xia;
Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems
2011 / IEEE / 978-1-4577-1484-9
By: Sandionigi, C.; Miele, A.; Bolchini, C.;
An impact analysis of gate resistance on static and dynamic dissipation of IGBT modules
2011 / IEEE / 978-1-4577-0321-8
By: Yao-Yu Duan; Yang-Jun Zhu; Shao-Wei Hu;
Improving the performance of an SOC design for network processing based on FPGA with PlanAhead
2011 / IEEE / 978-1-4577-0321-8
By: Yue Hao; Jiang-Yi Shi; Qing Guang; Li Lei; Kang Li;
Yield-award placement optimization for Switched-Capacitor analog integrated circuits
2011 / IEEE / 978-1-4577-1617-1
By: Chin-Long Wey; Pei-Wen Luo; Jwu-E Chen; Chien-Chih Huang;
Fast analog layout prototyping for nanometer design migration
2011 / IEEE / 978-1-4577-1400-9
By: Wei-Zen Chen; Chien-Hung Chen; Po-Cheng Pan; Tung-Chieh Chen; Hung-Ming Chen; Yi-Peng Weng;
Pseudo-functional testing for small delay defects considering power supply noise effects
2011 / IEEE / 978-1-4577-1400-9
By: Xiao Liu; Feng Yuan; Qiang Xu;
Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing
2011 / IEEE / 978-1-4577-1400-9
By: Yen-Hung Lin; Yih-Lang Li; Pan, D.Z.; Yong-Chan Ban;
Statistical analysis of EMI noise measurement for Flash Memory
2011 / IEEE / 978-95-318-4158-0
By: Chiu-Kuo Chen; Jia-Li Chang; Chung-Wei Kuo; Han-Nien Lin;
Temperature dependent wire delay estimation in floorplanning
2011 / IEEE / 978-1-4577-0516-8
By: Winther, A.T.; Vrudhula, S.; Nannarelli, A.; Wei Liu;
Design of a low power Delay Locked Loop based Clock and Data Recovery circuit
2011 / IEEE / 978-1-4577-1109-1
By: Khosla, M.; Kumar, V.;
On-chip circuit for massively parallel BTI characterization
2011 / IEEE / 978-1-4577-0115-3
By: Kaczer, B.; da Silva, M.B.; Groeseneken, G.; Wirth, G.I.; Van der Plas, G.;
Design-for-debug layout adjustment for FIB probing and circuit editing
2011 / IEEE / 978-1-4577-0152-8
By: Chao, M.C.-T.; Meng-Chen Wu; Tsung-Wei Chang; Kuo-An Chen; Chen, S.; Jing-Yang Jou;
Statistical thermal modeling and optimization considering leakage power variations
2012 / IEEE / 978-1-4577-2145-8
By: Yao-Wen Chang; Marculescu, D.; Yi-Lin Chuang; Da-Cheng Juan;
Enabling power density and thermal-aware floorplanning
2012 / IEEE / 978-1-4673-1111-3
By: Ziabari, A.; Ardestani, E.K.; Renau, J.; Shakouri, A.;
Voltage island-driven floorplanning considering level shifter placement
2012 / IEEE / 978-1-4673-0772-7
By: Wei-Yi Cheng; Jai-Ming Lin; Hsu, R.C.J.; Chung-Lin Lee;
An effecient level-shifter floorplanning method for Multi-voltage design
2011 / IEEE / 978-1-61284-193-9
By: Yoshimura, T.; Song Chen; Zhi Lin; Xiaolin Zhang;
Thermal considerations in high power microwave amplifiers design
2012 / IEEE / 978-1-4577-1929-5
By: Naeem, U.; Naz, H.; Shah, M.A.; Farooqui, M.F.;
Configuring algorithm for reconfigurable Network-on-Chip architecture
2012 / IEEE / 978-1-4577-1415-3
By: Bin Li; Huaxi Gu; Hui Ding; Keming Du;
Challenges and solutions in modern analog placement
2012 / IEEE / 978-1-4577-2081-9
By: Chi-Chen Peng; Chung-Che Hsieh; Ta-Yu Kuan; Tung-Chieh Chen;
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array
2012 / IEEE / 978-1-4577-2081-9
By: Kuen-Di Lee; Nan-Chun Lien; Wei Hwang; Shyh-Jye Jou; Ching-Te Chuang; Wei-Chiang Shih; Geng-Cing Lin; Hao-I Yang; Ming-Chien Tsai; Yi-Wei Lin; Shao-Cheng Wang;
A 6-bit 122 MS/s digital-to-analog converter for contactless applications in CMOS 90 nm technology
2012 / IEEE / 978-83-932075-8-9
By: Brzezinski, M.; Pleskacz, W.A.; Pomorski, T.;
A novel low-waveguide-crossing floorplan for fat tree based optical networks-on-chip
2012 / IEEE / 978-1-4577-1619-5
By: Jiang Xu; Zhehui Wang; Zhe Wang; Xuan Wang; Xiaowen Wu; Nikdast, M.; Weichen Liu; Wei Zhang; Yaoyao Ye;
Performance metrics and empirical results of a PUF cryptographic key generation ASIC
2012 / IEEE / 978-1-4673-2340-6
By: Sowell, R.; Meng-Day Yu; Devadas, S.; M'Raihi, D.; Singh, A.;
New method of multy-mode oscillations control in crystal resonators
2012 / IEEE / 978-1-4577-1820-5
By: Lepetaev, A.N.; Kosykh, A.V.;
Accurate process-hotspot detection using critical design rule extraction
2012 / IEEE / 978-1-4503-1199-1
By: Jiang, I.H.-R.; Sinha, S.; Ya-Chung Chan; Yen-Ting Yu; Chiang, C.;
Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology
2012 / IEEE / 978-1-4503-1199-1
By: Qiang Ma; Wong, M.D.F.; Hongbo Zhang;
Go Ahead: A Partial Reconfiguration Framework
2012 / IEEE / 978-1-4673-1605-7
By: Koch, D.; Beckhoff, C.; Torresen, J.;
Book reviews [8 books reviewed]
2014 / IEEE
Circuit layout and yield
1988 / IEEE
By: Kooperberg, C.;
Planar embedding: linear-time algorithms for vertex placement and edge orderings
1988 / IEEE
By: Swamy, M.N.S.; Thulasiraman, K.; Jayakumar, R.;
Interstitial redundancy: an area efficient fault tolerance scheme for large area VLSI processor arrays
1988 / IEEE
By: Singh, A.D.;
A routing model for the NCR GAPP
1988 / IEEE
By: Signorini, J.;
Rectangular dualization and rectangular dissections
1988 / IEEE
By: Kinnen, E.; Kozminski, K.A.;
A graph theoretic approach to single row routing problems
1988 / IEEE
By: Bhattacharya, B.B.; Sherwani, N.A.; Deogun, J.S.;
A problem on rectangular floorplans
1988 / IEEE
By: Hakimi, S.L.;
Area-efficient drawings of rectangular duals for VLSI floor-plan
1988 / IEEE
By: Tani, K.; Ariyoshi, H.; Shirakawa, I.; Tsukiyama, S.;
An analytical method for optimal module orientation
1988 / IEEE
By: Liu, C.L.; Yamada, M.;
Automatic building of graphs rectangularly dualisable for use in IC floorplanning
1988 / IEEE
By: Jabri, M.A.;
An O(n)-time standard cell placement algorithm using constrained multi-stage graph model
1988 / IEEE
By: Cho, H.G.; Kyung, C.M.;
A new floorplanning method with global routing based on functional partitioning
1988 / IEEE
By: Izumoto, H.; Ohmura, M.; Toshida, N.; Kikuno, T.; Fukii, T.;
On finding and modelling nested permutations in graphs
1988 / IEEE
By: Shiran, Y.;
On dual Eulerian paths and circuits in plane graphs
1988 / IEEE
By: Ueno, S.; Kajitani, Y.; Tsuji, K.;
A doughnut layout style for improved switching speed with CMOS VLSI gates
1989 / IEEE
By: Siferd, R.; Longway, C.;
On internal-external layouts
1989 / IEEE
By: Tollis, I.G.;
Performance limits of electrical interconnections to a high-speed chip
1988 / IEEE
By: Rainal, A.J.;
Thick-film circuit layout using the Magic layout editor
1988 / IEEE
By: Scoles, K.J.;
Algorithms for floorplan design via rectangular dualization
1988 / IEEE
By: Leinwand, S.M.; Yen-Tai Lai;
An algebraic expression to count the number of chips on a wafer
1989 / IEEE
By: Ferris-Prabhu, A.V.;
RELIANT: a reliability analysis tool for VLSI interconnect
1989 / IEEE
By: Frost, D.F.; Poole, K.F.;
An improved buffer for bioelectric signals
1989 / IEEE
By: Pallas-Areny, R.; Rosell, J.; Colominas, J.;
Finite element method applied to modeling crosstalk problems on printed circuit boards
1989 / IEEE
By: Costache, G.I.; Khan, R.L.;
A 200 MHz video amplifier system for high frequency monitor applications
1988 / IEEE
By: Page, R.W.;
Linear complexity algorithms for hierarchical routing
1989 / IEEE
By: Hachtel, G.D.; Morrison, C.R.;
Mismatch simulation for layout sensitive parameters of IC components and devices
1989 / IEEE
By: Tomaszewski, P.; Troster, G.;
On VHV-routing in channels with irregular boundaries
1989 / IEEE
By: Chen, H.H.; Vijayan, G.; Wong, C.K.;
An analytic model of printed circuit wiring distributions
1989 / IEEE
By: Schmidt, D.C.;
Knowledge-based analog circuit synthesis with flexible architecture
1988 / IEEE / 0-8186-0872-2
By: Li, Y.-N.; Chen, D.J.; Fung, A.H.; Sheu, B.J.;
Optimal routing of two rectangular blocks
1989 / IEEE
By: Breuer, M.A.; Chandrasekhar, M.S.;
Two new and 'more difficult' channel routing problems
1989 / IEEE
By: Deutsch, D.N.;
Analytical approaches to the combinatorial optimization in linear placement problems
1989 / IEEE
By: Chowdhury, S.;
Improved gate matrix layout
1989 / IEEE
By: Huang, S.; Wing, O.;
A new approach to topological via minimization
1989 / IEEE
By: Sarrafzadeh, M.; Lee, D.T.;
Via minimization in VLSI routing with movable terminals
1989 / IEEE
By: Bhattacharya, B.B.; Deogun, J.S.;
Gate dimension characterization using the inversion layer
1989 / IEEE / 0-87942-714-0
By: Freeman, G.; Lukaszek, W.;
Exact algorithms for multilayer topological via minimization
1989 / IEEE
By: Nakajima, K.; Kashiwabara, T.; Rim, C.S.;
Routing in general junctions
1989 / IEEE
By: Maddila, S.R.; Zhou, D.;
Performance prediction for adaptive quad tree graphical data structures
1989 / IEEE
By: De Pauw, W.; Weyten, L.;
The number of intersections between two rectangular paths
1989 / IEEE
By: Wang, Y.-L.; Chang, J.S.; Lee, R.C.T.;
Fast effective heuristics for the graph bisectioning problem
1990 / IEEE
By: Rao, V.B.; Saab, Y.G.;
Covering rectilinear polygons by rectangles
1990 / IEEE
By: Sahni, S.; Wu, S.-Y.;
A linear-time algorithm for routing in a convex grid
1990 / IEEE
By: Kaufmann, M.;
New algorithms for the rectilinear Steiner tree problem
1990 / IEEE
By: Wong, C.K.; Vijayan, G.; Ho, J.-M.;
Test generation for current testing (CMOS ICs)
1990 / IEEE
By: Nigh, P.; Maly, W.;
Yield modeling using the SPIROS redundancy planner
1989 / IEEE / 0-8186-9901-9
By: Fried, J.;
CMOS subnanosecond true-ECL output buffer
1990 / IEEE
By: Dikken, J.; Schumacher, H.-J.; Seevinck, E.;
Package design for a microwave laser driver
1988 / IEEE
By: Caggiano, M.F.;
On via minimization
1990 / IEEE
By: Barahona, F.;
Minimum rectangular partition problem for simple rectilinear polygons
1990 / IEEE
By: Tan, J.J.-M.; Liou, W.T.; Lee, R.C.T.;
Placement for reliability and routability of convectively cooled PWBs
1990 / IEEE
By: Osterman, M.D.; Pecht, M.;
A fast transistor-chaining algorithm for CMOS cell layout
1990 / IEEE
By: Hsieh, Y.-C.; Hwang, C.-Y.; Hsu, Y.-C.; Lin, Y.-L.;
On the placement of critical devices in analog integrated circuits
1990 / IEEE
By: Fornera, L.; Sackinger, E.;
A Gomory-Hu cut tree representation of a netlist partitioning problem
1990 / IEEE
By: Hadley, S.W.; Vannelli, A.;
A channelless layout for multilevel synthesis with compiled cells
1989 / IEEE / 0-8186-1971-6
By: Leveugle, R.; Saucier, G.; Abouzeid, P.;
A cost function based optimization technique for scheduling in data path synthesis
1989 / IEEE / 0-8186-1971-6
By: Woo, N.S.; Shin, H.;
Fault chip defect characterization for wafer scale integration
1990 / IEEE
By: Yung, M.; Buehler, M.G.; Allen, R.A.; Sayah, H.R.; Hannaman, D.J.;
An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures
1991 / IEEE
By: Pedersen, S.; Paaske, E.; Jorgensen, H.N.; Sparso, J.; Rubner-Petersen, T.;

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