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Topic: Circuit Architecture

Results

Distortion-Less Real-Time Spectrum Sniffing Based on a Stepped Group-Delay Phaser
2012 / IEEE
By: Caloz, C.; Gupta, S.; Deforge, B.; Repeta, M.; Badiere, D.; Nikfal, B.;
Spur Free Dynamic Range Prediction for Phased Array Receivers
2012 / IEEE
By: Buckwalter, J.F.; Gupta, A.K.;
Single event upset and multiple cell upset modeling in commercial bulk 65 nm CMOS SRAMs and flip-flops
2009 / IEEE / 978-1-4577-0493-2
By: Tavernier, C.; Roche, P.; Gasiot, G.; Uznanski, S.; Autran, J.-L.;
A passive Excess-Loop-Delay compensation technique for Gm-C based continuous-time �� modulators
2011 / IEEE / 978-1-61284-857-0
By: Seng-Pan U; Sai-Weng Sin; Yang Jiang; Chen-Yan Cai; Martins, R.P.;
A gain control Low Noise Amplifier for 24 GHz application
2011 / IEEE / 978-1-4244-9793-5
By: Ssu-Chieh Chan; Pou-Tou Sun; Ying-Jui Chuang;
A digital circuit for extracting singular points from fingerprint images
2011 / IEEE / 978-1-4577-1846-5
By: Arjona, R.; Baturone, I.;
A single-phase to three-phase AC/AC converter with regeneration and adjustable power factor
2011 / IEEE / 978-1-4577-0001-9
By: Gwo-Jen Chiou; Tsung-Cheng Chen; Chen-Chih Yang; Hsien-Te Chiu; Jeng-Yue Chen;
Current based sensor analog signal processing technique for extracting the feedback signal
2011 / IEEE / 978-1-4577-0167-2
By: Leitis, K.; Halim, T.;
Wide bandwidth GSM/WCDMA/LTE base station LNA with ultra-low sub 0.5 dB noise figure
2012 / IEEE / 978-1-4577-1155-8
By: Staudinger, J.; Yun Wei; Miller, M.; Hooper, R.;
Design and simulation of on-chip circuits for parallel characterization of ultrascaled transistors for BTI reliability
2014 / IEEE
By: Putcha, Vamsi; Groeseneken, Guido; Kaczer, Ben; Franco, Jacopo; Weckx, Pieter; Bury, Erik;
A Nyquist-rate adaptation algorithm for fractionally spaced equalizers
1988 / IEEE
By: Debus, W.; Siller, C.A.;
An adaptive, CMOS neural array for pattern association
1989 / IEEE / 0-8186-1918-x
By: Walker, M.; Akers, L.A.; Hassler, P.;
A monolithic 12-bit multiplying DAC for NTSC and HDTV applications
1989 / IEEE
By: Taylor, S.S.; Simpkins, S.; Martinez, C.G.;
Fault simulation of unconventional faults in CMOS circuits
1991 / IEEE
By: Ricco, B.; Damiani, M.; Olivo, P.; Favalli, M.;
A real-time experiment using a 50-neuron CMOS analog silicon chip with on-chip digital learning
1991 / IEEE
By: Salam, F.M.A.; Wang, Y.;
A model of neural circuits for programmable VLSI implementation
1989 / IEEE
By: Salam, F.M.A.;
A high-speed current-multiplexed sample-and-hold amplifier with low hold step
1991 / IEEE
By: Moraveji, F.;
On the design of CMOS digital output drivers with controlled dI/dt
1991 / IEEE / 0-7803-0050-5
By: Torelli, G.; Maloberti, F.;
The modified Alopex algorithm and its circuit architecture
1992 / IEEE / 0-7803-0803-4
By: Zhang Hang; Song Junde; Peng Yizhong;
Implementing a high-frequency pattern generator based on combinational merging
1992 / IEEE / 0-8186-3110-4
By: Zukowski, C.A.; Bai, Y.-W.;
Development of FET-switched induction accelerator cells for heavy-ion fusion recirculators
1993 / IEEE / 0-7803-1203-1
By: Hawkins, S.A.; Cravey, W.R.; Newton, M.A.; Ollis, C.W.; Kirbie, H.C.;
Nanoelectronic devices: opportunities and challenges
1993 / IEEE / 0-7803-1450-6
By: Kern, D.P.;
50-V LCD driver integrated in standard 5-V CMOS process
1994 / IEEE / 0-7803-1886-2
By: Ballan, H.; Valencic, V.; Declercq, M.; Hochet, B.; Deval, P.;
A systematic method for nonlinear analysis of a class of FET circuits
1993 / IEEE / 0-7803-1281-3
By: Radmore, P.M.; Haigh, D.G.; Losada, C.A.;
Analog VLSI chip for stereocorrespondence
1994 / IEEE / 0-7803-1915-X
By: Mahowald, M.;
Architectural descriptions for FPGA circuits
1995 / IEEE / 0-8186-7086-X
By: Singh, S.;
Design criteria for BJT amplifiers with low 1/f AM and PM noise
1995 / IEEE / 0-7803-2500-1
By: Ferre-Pikal, E.S.; Nelson, C.W.; Walls, F.L.;
Sensing circuit for on-line detection of delay faults
1996 / IEEE
By: Metra, C.; Favalli, M.;
Implementation of time-multiplexed CNN building block cell
1996 / IEEE / 0-8186-7373-7
By: Leong, P.H.W.; Lai, K.K.;
Readout electronics with calibration and on-line test for resistive sensor bridges
1996 / IEEE / 0-7803-3117-6
By: Machul, O.; Hosticka, B.J.; Brockherde, W.; Hammerschmidt, D.;
Fast, radiation-hard GaAs CHIGFET op amp
1993 / IEEE / 0-8186-3560-6
By: Pennington, T.; DiBitonto, D.; Subhani, K.F.; Stronczer, J.; Baier, S.;
Low-voltage companding current-mode integrators
1995 / IEEE / 0-7803-2570-2
By: Enz, C.; Punzenberger, M.;
A high speed Reed-Solomon decoder
1995 / IEEE / 0-7803-2612-1
By: Jin Su Chang; Seung Bae Choi; Moon Ho Lee;
A 3.3V 50MHz synchronous 16Mb flash memory
1995 / IEEE / 0-7803-2495-1
By: Frary, K.; Gullard, T.; Fackenthal, R.; Bashir, A.; Bauer, M.; Mills, D.; Tsang, J.; Sweha, S.; Sambandan, S.; Rozman, R.; Rashid, M.; Pudar, S.; Leak, D.; Kwong, P.; Javanifard, J.; Haid, C.;
Some physical limits in switching technologies
1996 / IEEE / 0-7803-2916-3
By: Shu-Ang Zhou;
Implementation and design of a new model of neural network with application to typographical character recognition
1996 / IEEE / 0-7803-3259-8
By: Montes, M.; Lopez, O.; Gomez, J.M.; Herms, A.; Juvells, I.; Bota, S.A.;
A methodology for high level synthesis of high performance DSP structures targetting FPGAs
1996 / IEEE / 7-5439-0940-5
By: Al-Khalili, A.; Haroun, B.; Shehata, S.;
A four-channel ADC on a VME board
1990 / IEEE
By: Ponchia, R.; Bassato, G.; Boiano, C.; Bassini, R.;
A performance-driven macro-block placer for architectural evaluation of ASIC designs
1995 / IEEE / 0-7803-2707-1
By: Onodera, H.; Moshnyaga, V.G.; Mori, Y.; Tamaru, K.;
Guidelines for designing BJT amplifiers with low 1/f AM and PM noise
1997 / IEEE
By: Walls, F.L.; Ferre-Pikal, E.S.; Nelson, C.W.;
Neural spectral composition for function approximation
1997 / IEEE / 0-7803-4122-8
By: Piuri, V.; Pelagotti, A.;
High-throughput communication network for online subscriber testing station
1997 / IEEE / 0-7803-4162-7
By: Zibinch, Dz.; Zagursky, V.;
Radiation effects in advanced microelectronics technologies
1997 / IEEE / 0-7803-4071-X
By: Johnston, A.H.;
Rapid design of a single chip adaptive beamformer
1998 / IEEE / 0-7803-4997-0
By: Walke, R.; McCanny, J.; Woods, R.; Lightbody, G.; Trainor, D.; Hu, Y.;
Neuron-MOS continuous-time winner-take-all circuit for intelligent data processing
1998 / IEEE / 0-7803-4316-6
By: Morimoto, T.; Ohmi, T.; Shibata, T.;
An analog VLSI which emulates biological vision
1998 / IEEE / 0-7803-4316-6
By: Yagi, T.; Kameda, S.; Hayashida, Y.;
InP-based HFETs and RTDs for high speed digital circuitry
1998 / IEEE / 0-7803-4900-8
By: Bertenburg, R.M.; Janssen, G.; Brennemann, A.; Pacha, C.; Auer, U.; Brockerhoff, W.; Tegude, F.-J.; Prost, W.; Goser, K.F.; Bushehri, E.;
An ultralow-power-consumption, high-speed, GaAs 256/258 dual-modulus prescaler IC
1999 / IEEE
By: Yamazaki, J.; Ishikawa, M.; Tokushima, M.; Wada, S.; Maeda, T.; Fujii, M.;
Multirate as a hardware paradigm
1999 / IEEE / 0-7803-5041-3
By: Velazquez, S.R.; Stevens, K.S.; Suter, B.W.; Nguyen, T.;
Multi-mode impedance synthesis for subscriber line applications
1999 / IEEE / 0-7803-5471-0
By: Youngblood, D.L.;
Equivalence classes of clone circuits for physical-design benchmarking
1999 / IEEE / 0-7803-5471-0
By: Rose, J.; Hutton, M.D.;
A current-mode implementation of a traveling wave amplifier model similar to the cochlea
1999 / IEEE / 0-7803-5471-0
By: Hubbard, A.E.; Zhang, Q.; Yang, Z.; Hinck, T.;
Design of a high speed 12-bit subranging A/D converter
1998 / IEEE / 0-7803-4306-9
By: Wang Ruoxu;
Distortion in analog VLSI networks for image filtering
1999 / IEEE
By: Kwok Fai Hui; Shi, B.E.;
A 110-dB-THD, 18-mW DAC using sampling of the output and feedback to reduce distortion
1999 / IEEE
By: Thomsen, A.; Lee, W.L.; Wang, L.; Kasha, D.B.;
Linearization method for fast voltage-to-current converters
2000 / IEEE / 0-7803-6309-4
By: Paulus, C.; Thewes, R.;
A new architecture to compute the discrete cosine transform using the quadratic residue number system
2000 / IEEE / 0-7803-5482-6
By: Garcia, A.; Ramirez, J.; Lloris, A.; Parrilla, L.; Fernandez, P.G.;
Performance optimization for high-order continuous-time /spl Sigma//spl Delta/ modulators with extra loop delay
2000 / IEEE / 0-7803-5482-6
By: Draper, J.; Choma, J., Jr.; Luh, L.;
Vector delta-sigma modulation with integral shaping of hardware-mismatch errors
2000 / IEEE / 0-7803-5482-6
By: Scholnik, D.P.; Coleman, J.O.;
A method for stability and performance analysis of low oversampling ratio higher order sigma delta noise shaper architectures
1999 / IEEE / 0-7803-5491-5
By: Gothenberg, A.; Tenhunen, H.; Bingxin Li;
An analysis of dynamic element matching digital to analog converters
1999 / IEEE / 0-7803-5491-5
By: Bruce, J.W.; Stubberud, P.;
Analysis and design of a family of low-power class AB operational amplifiers
2000 / IEEE / 0-7695-0843-X
By: Silveira, F.; Flandre, D.;
An 8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique
2001 / IEEE
By: Ming-Huang Liu; Shen-Iuan Liu;
Design considerations for band-pass sigma delta modulators
2001 / IEEE / 0-7803-6685-9
By: Singh, P.K.; Maloberti, F.;
A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic
2001 / IEEE / 0-7803-6685-9
By: Mehrez, H.; Bajot, Y.; Dumonteix, Y.;
VLSI implementation of a neural network for solving linear second order parabolic PDE
2000 / IEEE / 0-7803-6475-9
By: Xia, B.; Moon, S.T.; Sanchez-Sinencio, E.; Gunhee Han; Spencer, R.G.;
Triple-push oscillator approach: theory and experiments
2001 / IEEE
By: Yu-Lung Tang; Huei Wang;
A high speed 0.25 /spl mu/m 64-bit CMOS adder design
2001 / IEEE / 0-7803-6677-8
By: Ye Yi-zheng; Lai Feng-chang; Mao Zhi-gang; Sun Xu-guang;
A high-performance RF bandpass prefilter
2001 / IEEE / 0-7803-6677-8
By: Li Yong-ming; Lu Chao;
Application of logical effort techniques for speed optimization and analysis of representative adders
2001 / IEEE / 0-7803-7147-X
By: Hoang Dao; Oklobdzija, V.G.;
Competitively coupled orientation selective cellular neural networks
2002 / IEEE
By: Boahen, K.; Shi, B.E.;
EHBSim: Matlab-based multitone excited nonlinear circuit simulation program
2001 / IEEE / 0-7803-7065-1
By: da Cunha Brito, L.; de Carvalho, P.H.P.;
A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture
2002 / IEEE / 0-7695-1700-5
By: Satoh, A.; Morioka, S.;
Organic field emission device integrated with organic transistor
2002 / IEEE / 0-7803-7462-2
By: Kymissis, I.; Akinwande, A.I.;
New architecture for high data rate turbo decoding of product codes
2002 / IEEE / 0-7803-7632-3
By: Cuevas, J.; Pyndiah, R.; Kerouedan, S.; Adde, P.;
A low-power entropy-coding analog/digital converter with integrated data compression
2003 / IEEE / 0-7803-7995-0
By: Peck, R.; Schroeder, D.;
A 20 Gb/s 82mW one-stage 4:1 multiplexer in 0.13 /spl mu/m CMOS
2003 / IEEE / 0-7803-7995-0
By: Wohlmuth, H.-D.; Kehrer, D.;
Design centering using an approximation to the constraint region
2004 / IEEE
By: Wojciechowski, J.M.; Zamlynski, K.; Opalski, L.J.;
A 0.13 /spl mu/m CMOS serializer for data and trigger optical links in particle physics experiments
2003 / IEEE / 0-7803-8257-9
By: Marchioro, A.; Cervelli, G.; Moreira, P.;
Low voltage and low power aspects of data converter design
2004 / IEEE / 0-7803-8478-4
By: Qiuting Huang;
Fault-tolerant PLA-style circuit design for failure-prone nanometer CMOS and quantum device technologies
2004 / IEEE / 0-7803-8359-1
By: Schmid, A.; Leblebici, Y.;
Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers
2005 / IEEE
By: Lok-Kee Ting; Cowan, C.F.N.; Woods, R.;
A temperature-dithering closed-loop interface circuit for a scanning thermal microscopy system
2005 / IEEE
By: Gianchandani, Y.B.; Joohyung Lee;
A design based yield and redundancy model for high density dualport SRAM on 90nm technology
2004 / IEEE / 0-7803-8511-X
By: Tao Peng; Iandolo, W.; Landry, G.;
The DIALOG chip in the front-end electronics of the LHCb muon detector
2004 / IEEE / 0-7803-8700-7
By: Cadeddu, S.; Lai, A.; Deplano, C.;
The SYNC chip in the front-end electronics of the LHCb muon detector
2004 / IEEE / 0-7803-8700-7
By: Lai, A.; Fois, E.; Deplano, C.; De Leo, V.; Cadeddu, S.;
Organic field emission device integrated with organic transistor
2005 / IEEE
By: Akinwande, A.I.; Kymissis, I.;
How much mismatch should be simulated in the high density SRAM sense amplifier design
2005 / IEEE / 0-7803-8803-8
By: Tao Peng;
Broad-band 180/spl deg/ phase shifters using integrated submillimeter-wave Schottky diodes
2005 / IEEE
By: Weikle, R.M., II; Crowe, T.W.; Haiyong Xu; Midkiff, J.C.; Zhiyang Liu;
A VLSI GFP frame delineation circuit
2006 / IEEE / 0-7695-2533-4
By: Xin Yang; Sezer, S.; Toal, C.;
An integrated 6.2-11GHz SiGe inductorless injection locked frequency divider
2005 / IEEE / 2-9600551-2-8
By: Haslett, J.W.; Nakaska, J.K.;
FSM decomposition for power gating design automation in sequential circuits
2005 / IEEE / 0-7803-9210-8
By: Yici Cai; Bin Liu; Xianlong Hong; Jinian Bian; Qiang Zhou;
Reviews and Prospects of Nanoscale SRAMs
2006 / IEEE / 1-4244-0097-X
By: Osada, K.;
Adaptive Interpolation Algorithm for Real-time Image Resizing
2006 / IEEE / 0-7695-2616-0
By: Xuecheng Zou; Jianping Xiao; Xu Guo; Zhenglin Liu;
Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density
2006 / IEEE / 0-7803-9490-9
By: Leblebici, Y.; Schmid, A.; Stanisavljevic, M.;
Propagating SET Characterization Technique for Digital CMOS Libraries
2006 / IEEE
By: Baze, M.P.; McMorrow, D.; Massengill, L.; Amusan, O.A.; Wert, J.; Witulski, A.; Hubert, M.G.; Clement, J.W.;
A Novel Analog Decision-Feedback Equalizer for 10-Gb/sec Multi-Mode Fiber Dispersion Compensation
2007 / IEEE / 1-4244-0687-0
By: Kim, H.; Bien, F.; Chandramouli, S.; Laskar, J.; Scholz, C.; Gebara, E.;
Comparison of Two Pole-Zero Cancellation Circuits for Fast Charge Sensitive Amplifier in CMOS Technology
2007 / IEEE / 83-922632-4-3
By: Grybos, P.; Szczygiel, R.; Maj, P.;
A Study on Frequency Scalability for Integrated Imaging Radiometer Receivers Based on Subharmonic Self-Oscillating Mixers
2007 / IEEE / 1-4244-1448-2
By: Winkler, S.A.; Stelzer, A.; Ke Wu;
Soft IP Core Implementation of Recursive Least Squares Filter using Only Multplicative and Additive Operators
2007 / IEEE / 978-1-4244-1059-0
By: Francey, J.; Woods, R.; Lightbody, G.;

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