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Topic: Buried Channel

Results

Enhanced Programming and Erasing Speeds in P-Channel Charge-Trapping Flash Memory Device With SiGe Buried Channel
2012 / IEEE
By: Ming-Jinn Tsai; Tien-Ko Wang; Jen-Wei Cheng; Yi-Chuen Jian; Kuei-Shu Chang-Liao; Li-Jung Liu;
Two-phase charge coupled linear imaging devices with self-aligned implanted barrier
1974 / IEEE
By: Choong-Ki Kim;
An Investigation of Growth and Properties of Si Capping Layers Used in Advanced SiGe/Ge Based pMOS Transistors
2012 / IEEE / 978-1-4577-1865-6
By: Vandervorst, W.; Vanherlee, W.; Mitard, J.; Witters, L.; Dekoster, J.; Caymax, M.; Hikavyy, A.; Loo, R.;
Thermal effects in scanning acoustic microscopy for fine resolution applications
1994 / IEEE
By: Griffel, G.; Kenyon, A.J.; Golan, G.; Pitt, C.W.;
A 1-10 GHz interface engineered SiN/sub x//InP/InGaAs HIGFET technology
1996 / IEEE / 0-7803-3283-0
By: Masut, R.A.; Bensaada, A.; Mihelich, P.; Tazlauanu, M.; Sundararaman, C.S.;
Polysilicon gate with depletion-or-metallic gate with buried channel: what evil worse ?
1999 / IEEE / 0-7803-5410-9
By: Skotnicki, T.; Josse, E.;
1/f noise characterization of deep sub-micron dual thickness nitrided gate oxide n- and p-MOSFETs
1999 / IEEE / 0-7803-5410-9
By: Matloubian, M.; Li-Ming Hwang; D'Souza, S.; Kempf, P.; Martin, S.; Bhattacharya, S.; Hong Wu; Joshi, A.; Sherman, P.;
Stress induced leakage current analysis via quantum yield experiments
2000 / IEEE
By: Monroe, D.; Bude, J.; Alam, M.; Ghetti, A.; Vaidya, H.; Sangiorgi, E.;
Large area 4H-SiC power MOSFETs
2001 / IEEE / 4-88686-056-7
By: Agarwal, A.; Saks, N.; Palmour, J.; Lipkin, L.; Das, M.; Sei-Hyung Ryu;
Short-channel modeling of bulk accumulation MOSFETs
2004 / IEEE
By: Lihui Wang; Austin, B.L.; Murali, R.; Meindl, J.D.;
The Study of PMOS Vth Distribution Using Process and Device Simulations and C-V Measurements
2005 / IEEE / 1-4244-0049-X
By: Jevtic, M.; Hadzi-Vukovic, J.;
Enhancement-Mode Buried-Channel $\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As/In}_{0.52}\hbox{Al}_{0.48}\hbox{As}$ MOSFETs With High- $\kappa$ Gate Dielectrics
2007 / IEEE
By: Sun, Y.; Kiewra, E.W.; Koester, S.J.; Ruiz, N.; Callegari, A.; Fogel, K.E.; Forrest, S.R.; Fompeyrine, J.; Webb, D.J.; Locquet, J.-P.; Sousa, M.; Germann, R.; Shiu, K.T.; Sadana, D.K.;
A 50nm high-k poly silicon gate stack with a buried SiGe channel
2007 / IEEE / 1-4244-0584-X
By: Veloso, A.; Cho, H.-J.; Hoffmann, T.; Jakschik, S.; Biesemans, S.; Absil, P.; Loo, R.; Severi, S.; Eneman, G.; Potter, M.d.; Inoue, A.; Sorada, H.;
SiGe-Channel Confinement Effects for Short-Channel PFETs With Nonbandedge Gate Workfunctions
2007 / IEEE
By: Tekleab, D.; Taylor, W.J.; Loiko, K.; Verret, E.; Capasso, C.; Winstead, B.; Samavedam, S.B.; Foisy, M.;
Low-Mass PECVD Oxynitride Gas Chromatographic Columns
2007 / IEEE
By: Wise, K.D.; Agah, M.;
Formation of Silicon Nanopores and Nanopillars by a Maskless Deep Reactive Ion Etching Process
2007 / IEEE / 1-4244-0841-5
By: Chan, P.C.H.; Chunhua Feng; Zhiyong Xiao; I-Ming Hsing;
n- and p-channel TaN/HfO2 MOSFETs on GaAs substrate using a germanium interfacial passivation layer
2007 / IEEE / 978-1-4244-1101-6
By: Lee, J.C.; Zhao, H.; Yum, J.; Park, S.; Hyoung-Sub Kim; Zhang, M.; Feng Zhu; Injo Ok;
Design Methodology of Body-Biasing Scheme for Low Power System LSI With Multi- $V_{\rm th}$ Transistors
2007 / IEEE
By: Imai, K.; Goto, Y.; Yamagata, Y.; Akiyama, Y.; Yasuda, Y.;
High-Performance $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ -Channel MOSFETs With High-$\kappa$ Gate Dielectrics and
2009 / IEEE
By: Shahidi, G.G.; Sadana, D.K.; Fogel, K.E.; Bucchignano, J.J.; de Souza, J.P.; Kiewra, E.W.; Sun, Y.;
Equivalent circuit model for capacitances in PN varactors with buried channel
2009 / IEEE / 978-1-4244-2838-0
By: Marrero-Martin, M.; Hernaindez, A.; Gonzalez, B.; Garcia, J.;
CMOS-compatible three dimensional buried channel technology (3DBCT)
2009 / IEEE / 978-1-4244-4190-7
By: Agah, M.; Renaghan, L.; Zellner, P.;

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