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X86-ARM binary hardware interpreter
By: Akkary, H.; Karaki, H.; Shahidzadeh, S.;
2011 / IEEE / 978-1-4577-1846-5
This item was taken from the IEEE Conference ' X86-ARM binary hardware interpreter ' In the computer hardware industry, there are currently two highly successful instruction set architectures (ISAs): the CISC x86 ISA which is an established standard architecture in the personal computer and server markets, and the RISC ARM ISA which has become the standard in the fast growing ultra-mobile computing devices market, such as smart-phones and tablets. Program binaries that run on one standard ISA cannot be used on the other without recompiling the source application. We are investigating the technical feasibility of designing energy-efficient universal computing platform that can run both x86 and ARM binaries. In this paper, we present results from the initial stage of our work, which involves designing multiple instruction set architecture processor (MISA). Our MISA architecture enhances an ARM processor pipeline with an x86 decoder that maps at run time each x86 CISC instruction into one or more standard ARM instructions. We describe XAM, our X86-to-ARM binary interpreter hardware, and present performance results using the ARM SimpleScalar microarchitecture simulator and a set of synthetic benchmarks including Dhrys tone2.1.
Multiple Instruction Set Architecture Processor
X86-arm Binary Hardware Interpreter
Computer Hardware Industry
Ultramobile Computing Devices
Energy-efficient Universal Computing Platform
Cisc X86 Isa