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A Simulation Based Buffer Sizing Algorithm for Network on Chips

By: Benini, L.; Kamakoti, V.; Murali, S.; Kumar, M.P.; Kumar, A.S.; De Micheli, G.;

2011 / IEEE / 978-1-4577-0803-9

Description

This item was taken from the IEEE Conference ' A Simulation Based Buffer Sizing Algorithm for Network on Chips ' Buffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnect. Hence, reducing the buffering overhead of Networks on Chips (NoCs) is an important problem. For application-specific designs, the network utilization across the different links and switches is non-uniform, thereby requiring a buffer sizing approach that tackles the non uniformity. Moreover, congestion effects that occur during network operation needs to be captured when sizing the buffers. To this end, we propose a two-phase algorithm to size the switch buffers in NoCs. Our algorithm considers both the static (based on bandwidth and latency requirements) and dynamic (based on simulation) effects when sizing buffers. Our experiments show that the application of the algorithm results in 42% reduction in amount of buffering required to meet the application constraints when compared to a standard buffering approach.