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Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper

By: Meloni, P.; Raffo, L.; Secchi, S.;

2010 / IEEE / 978-1-4244-6471-5

Description

This item was taken from the IEEE Conference ' Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper ' The complexity of modern interconnect architecture design requires highly accurate and rapid simulation environments. FPGA-based emulators have been proposed as an alternative to software cycle-accurate simulators, preserving maximum accuracy and reasonable simulation times. However, the potential speedup is reduced by the time overhead needed for RTL synthesis/implementation. This paper proposes runtime reconfiguration of the architecture to push the hardware emulation one step further, by reducing the number of FPGA implementation processes to be run. To this aim, this work presents an algorithm that synthesizes, for a set of candidate architectural configurations, a connection topology capable of reconfiguring itself via software to emulate all the design space points under evaluation. We present the actual reconfiguration algorithm, the CAD tools and the hardware mechanisms that implement it. The design capabilities provided by this approach are evaluated with a design space exploration case study.