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A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory

By: Sung-Jin Choi; Yang-Kyu Choi; Moongyu Jang; Dong-Il Moon; Sungho Kim; Jin-Woo Han;

2010 / IEEE / 978-1-4244-5450-1

Description

This item was taken from the IEEE Conference ' A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory ' A d2opant s2egregated S2chottky b2arrier (DSSB) TFT SONOS device is demonstrated for the application of 3D TFT logic devices and flash memory. To apply the DSSB to 3D TFT flash memory, a novel spacer-free structure is successfully implemented. The DSSB TFT SONOS shows a good distribution of programmed VT by one-time programming with high-speed (a VT shift of 2.9 V @ 32 ns) due to the use of a unique local injection of carriers from the DSSB S/D junctions and it is not affected by grain boundaries. Moreover, the program speed is accelerated by reduction of the fin width owing to the enhanced field.