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Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits
By: Bolkhovsky, V.; Hu, W.; Suntharalingam, V.; Soares, A.M.; Donnelly, J.P.; Berger, R.; Mahoney, L.J.; Oakley, D.C.; Chapman, D.C.; Knecht, J.M.; Yost, D.-R.; Chen, C.L.; Shaver, D.C.; Keast, C.L.; Wheeler, B.D.;
2009 / IEEE / 978-1-4244-4511-0
This item was taken from the IEEE Conference ' Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits ' In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 �1024 diode array with 8-�m pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.
Indium Gallium Arsenide
Iii-v Semiconductor Materials
Integrated Circuit Interconnections
Silicon On Insulator Technology
Size 150 Mm
Silicon-on-insulator Readout Circuits
Hybridize Inp-based Image Sensor Arrays
Si Readout Circuits
Wafer-scale 3d Integration