Use this resource - and many more! - in your textbook!
AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.
Reliable through silicon vias for 3D silicon applications
By: Liptak, R.; Tsang, C.; Shapiro, M.; Dang, B.; Andry, P.; Interrante, M.; Griffith, J.; Knickerbocker, J.; Berger, D.; Truong, V.; Guerin, L.; Sprogis, E.;
2009 / IEEE / 978-1-4244-4492-2
This item was taken from the IEEE Conference ' Reliable through silicon vias for 3D silicon applications ' The use of through silicon vias (TSVs) is required to implement 3D chip stacking technology. This work explores a method to fabricate highly reliable TSVs that is compatible with CMOS processing. The key feature of the TSVs is a redundant tungsten bar with a high temperature thermal oxide insulating liner. Care must be taken when exposing the TSVs from the back side so that material is not left on the surface that can cause a leakage path to the silicon wafer. TSVs were produced with that had no fails through standard JDEC testing.
Power System Reliability
High Temperature Thermal Oxide Insulating Liner
3d Chip Stacking Technology
3d Silicon Applications
Through Silicon Vias
Cmos Integrated Circuits
Integrated Circuit Reliability