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Upside-down FETS

By: Patel, J.; Topol, A.W.; Steen, S.E.; Frnak, D.J.; La Tulipe, D.C.; Sleight, J.W.; Ramakrishnan, L.;

2008 / IEEE / 978-1-4244-1954-8

Description

This item was taken from the IEEE Conference ' Upside-down FETS ' To address key challenges in transistor scaling [1,2], we have used 3D oxide bonding technology in a new way, to fabricate CMOS devices and circuits in which the gate is on the opposite side of the channel from the contacts between the FET and the first wiring level (M1). That is, the FET is upside down com pared to conventional CMOS technology (Fig. 1). For device scaling beyond the 45nm node the space between densely packed adjacent gates has be come so small that contacts (CA) between source/ drain salicide and M1 cause significant parasitic capacitance to the gate (Fig.2). In addition, simu lations show that as CA metallurgy disrupts stress liner continuity, it significantly reduces the stress enhanced drive current of the FETs [3]. Finally, metallization of high aspect CA holes is challenging, and accurate lithographic definition is quite difficult amid the gate topology. Such scaling related issues may be eliminated by the upside-down FET (UFET) design in which the CA contacts and wiring levels are placed on the back side of the FET. We also would argue that this new transistor geometry would offer significant performance advantage for the 22nm node and beyond. This experimental demonstration of the first successful use of 3D processing techniques to enhance conventional PDSOI devices provides a new venue to enable future generations of CMOS scaling.