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Layout-aware through-process circuit analysis

By: Ditlow, G.; Ziegler, M.; Singh, R.; Lavin, M.; Jin-Fuw Lee; Fook-Luen Heng;

2007 / IEEE / 978-1-4244-1277-8

Description

This item was taken from the IEEE Conference ' Layout-aware through-process circuit analysis ' In the post-90nm era, due to the advent of low-K1 lithography, variability of circuit parameters, such as effective gate-length and gate-width, is increasing. In this paper, we illustrate how we perform layout aware through process circuit analysis using simulated wafer contours and present results for a full-custom 4:2 compressor circuit.