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3D Chip Stacking Technology with Low-Volume Lead-Free Interconnections

By: Maria, J.; Dang, B.; Andry, P.S.; Sakuma, K.; Knickerbocker, J.U.; Horton, R.; Tsang, C.K.; Kang, S.K.; Polastre, R.; Sprogis, E.; Webb, B.; Wright, S.L.; Patel, C.;

2007 / IEEE / 1-4244-0984-5

Description

This item was taken from the IEEE Conference ' 3D Chip Stacking Technology with Low-Volume Lead-Free Interconnections ' In this paper a three-dimensional (3D) chip stacking technology using fine-pitched interconnects with lead-free solder is described. Different interconnect metallurgies such as Cu/Ni/In, Cu/In and Cu/Sn were considered and the bonding conditions to optimize the bonding parameters were determined. The effect of intermetallic compound (IMC) formation on the mechanical properties of the joins is discussed. Unlike standard 100-micron C4 solder balls, very small solder volumes (< 6 microns high) were investigated. The mechanical properties were evaluated by shear and impact shock testing, while scanning electron microscopy (SEM) and optical microscopy were used to study the morphology of the IMC layers in solder joins before and after annealing. It was found that Cu/Ni/In and Cu/In interconnections have slightly lower shear strength per bump. While these values were lower than the Cu/Sn joins, the Cu/Ni/In chips passed the impact shock test for a simulated heat sink mass of 27g/cm2. The reasons for the differences in reliability of these metallurgies are discussed. 3D chip stacking using two-layers of chips with fine-pitch lead-free interconnects was demonstrated. The resistance of link chains comprising through-vias, lead-free interconnects and Cu links were measured using a 4-point probing method. The average resistance of the through-via including the lead-free interconnect was 21 m¿.