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Reliability Support for On-Chip Memories Using Networks-on-Chip
2006 / IEEE / 978-0-7803-9706-4
This item was taken from the IEEE Conference ' Reliability Support for On-Chip Memories Using Networks-on-Chip ' As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. One of the most critical elements that affect the correct behavior of the system is the unreliable operation of on-chip memories. In this paper we present a novel solution to enable fault tolerant on-chip memory design at the system level for multimedia applications, based on the Network-on-Chip (NoC) interconnection paradigm. We transparently keep backup copies of critical data on a reliable memory; upon a fault event, data is fetched from the backup copy in hardware, without any software intervention. The use of a NoC backbone enables an efficient design which is modular, scalable and efficient. We proceed to demonstrating its effectiveness with two real-life application case studies, and explore the performance under varying architectural configurations. The overhead to support the proposed approach is very small compared to non-fault tolerant systems, i.e. no negative performance impact and an area increase dominated by that of just the backup storage itself.
Fault Tolerant On-chip Memory Design
Fault Tolerant Systems