Use this resource - and many more! - in your textbook!
AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.
A floating-gate programmable array of silicon neurons for central pattern generating networks
2006 / IEEE / 0-7803-9389-9
This item was taken from the IEEE Conference ' A floating-gate programmable array of silicon neurons for central pattern generating networks ' A new central pattern generator chip with 24 silicon neurons and reprogrammable connectivity is presented. The 3mm /spl times/ 3mm chip fabricated in a 3M2P 0.5/spl mu/m process contains 1032 synapses, each with multiple floating gates for storing parameters governing synaptic strength and polarity. Every neuron includes a dendritic compartment with 12 externally-addressable synaptic inputs and 24 recurrent synaptic inputs, enabling construction of a fully-interconnected network with sensory feedback from off-chip elements. In addition to describing the chip architecture and neuron circuits, preliminary results from single oscillating neurons and pairs of phase-locked neurons are shown. This work represents the realization of a design presented at ISCAS'05, and an improvement over our 2nd generation CPG chip presented at ISCAS'04.
Central Pattern Generating Networks
Floating-gate Programmable Array
Field Programmable Gate Arrays
Multiple Floating Gates