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Design-Technology Interface: What will replace design rules for DDSM?

By: Lavin, M.;

2006 / IEEE / 1-4244-0097-X


This item was taken from the IEEE Conference ' Design-Technology Interface: What will replace design rules for DDSM? ' It is now well-accepted that CMOS technology has entered a new era where the rapid, steady quantitative scaling of performance, density, etc. appears to be slowing, and is subject to new impediments (noise, static and dynamic power) as well as qualitative, sometimes disruptive change in processes, materials, and devices. One of the main contributors to this slowing and complication is the increasing impact of variability. What I want to discuss in this talk is how variability also impacts the interface between chip design and technology development. Historically, this interface was represented by design rules and device/wire models that scaled smoothly over time; this was reflected by the fact that IBM's processor technologies from the � micron node down to the 130nm node used a (mostly) stable set of scalable design rules and circuit models in which there was a single "" NRN"" dimension of variability. Going forward, it is clear that the models and the design tools that use them will have to capture a more complete understanding of systematic and random variability, and conventional design rules will have to be replaced by other means for representing to designers what the new technologies are (and are not) capable of. I will spend most of my talk describing some potential replacements for conventional design rules.