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An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration
2006 / IEEE / 3-9810801-1-4
This item was taken from the IEEE Conference ' An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration ' In recent years, increasing manufacturing density has allowed the development of Multi-Processor Systems-on-Chip (MPSoCs). Application-Specific Instruction Set Processors (ASIPs) stand out as one of the most efficient design paradigms and could be especially effective as SoC computing engines. However, multiple hurdles which are hindering the productivity of SoC designers and researchers must be solved first. Among them, the difficulty of thoroughly exploring the design space by simultaneously sweeping axes like processing elements, memory hierarchies and chip interconnect fabrics. We tackle this challenge by proposing an integrated approach where state-of-the-art platform modeling infrastructures, at the IP core level and at the system level, meet to provide the designer with maximum openness and flexibility in terms of design space exploration.
Design Space Exploration
Application-specific Instruction Set Processors
Platform Modeling Infrastructures
Ip Core Level
Application Specific Processors
Integrated Circuit Interconnections
Integrated Open Framework