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Stable SRAM cell design for the 32 nm node and beyond

By: Topol, A.W.; McNab, S.J.; Sekaric, L.; Montoye, R.K.; Sleight, J.W.; Dennard, R.H.; Adams, C.D.; Hergenrother, J.; Fried, D.M.; Chang, L.; Haensch, W.; Guarini, K.W.;

2005 / IEEE / 4-900784-00-1

Description

This item was taken from the IEEE Conference ' Stable SRAM cell design for the 32 nm node and beyond ' SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. 6T-SRAM can be optimized for stability by choosing the cell layout, device threshold voltages, and the /spl beta/ ratio. 8T-SRAM, however, provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling. We demonstrate the smallest 6T (0.124/spl mu/m/sup 2/ half-cell) and full 8T (0.1998/spl mu/m/sup 2/) cells to date.