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/spl times/pipes Lite: a synthesis oriented design library for networks on chips

By: Stergiou, S.; De Micheli, G.; Bertozzi, D.; Raffo, L.; Carta, S.; Angiolini, F.;

2005 / IEEE / 0-7695-2288-2

Description

This item was taken from the IEEE Conference ' /spl times/pipes Lite: a synthesis oriented design library for networks on chips ' The limited scalability of current bus topologies for systems on chips (SoCs) dictates the adoption of networks on chips (NoCs) as a scalable interconnection scheme. Current SoCs are highly heterogeneous in nature, denoting homogeneous, preconfigured NoCs as inefficient drop-in alternatives. While highly parametric, fully synthesizeable (soft) NoC building blocks appear as a good match for heterogeneous MPSoC architectures, the impact of instantiation-time flexibility on performance, power and silicon cost has not yet been quantified. The paper details /spl times/pipes Lite, a design flow for automatic generation of heterogeneous NoCs. /spl times/pipes Lite is based on highly customizable, high frequency and low latency NoC modules, that are fully synthesizeable. Synthesis results provide modules that are directly comparable, if not better, than the current published state-of-the-art NoCs in terms of area, power latency and target operating frequency measurements.