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Power-smart system-on-chip architecture for embedded cryptosystems

By: Gregori, S.; Vahedi, H.; Muresan, R.; Zhanrong, Y.;

2005 / IEEE / 1-59593-161-9

Description

This item was taken from the IEEE Conference ' Power-smart system-on-chip architecture for embedded cryptosystems ' In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provides support for masking these channels by controlling, in real-time, the power and the current consumption of a system to predefined programmable values. The main components of the architecture are a processor core, a current sensor module, a dynamically controlled power supply module, a clock frequency control module, and a current injection module. Real-time current measurements and power-aware voltage control are used in closed loop architecture to regulate and minimize the total power consumption of the system. Simulation results show that the current consumption of the system can be regulated to a reference level with reduced power-to-security trade off (power overhead less than 12% of the total power).