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CMOS discrete-time chaotic circuit for low-power embedded cryptosystems

By: Gregori, S.; Cabrini, A.;

2005 / IEEE / 0-7803-9197-7

Description

This item was taken from the IEEE Conference ' CMOS discrete-time chaotic circuit for low-power embedded cryptosystems ' We designed a discrete-time chaotic signal generator for low-power embedded cryptosystems. In these systems, an unpredictable source of random numbers is the key element to ensure security. In this paper we show how to design and use an integrated chaotic circuit for random number generation. The proposed circuit consists of a non linear function block, a S/H circuit, and a comparator. It is designed in 0.18-/spl mu/m CMOS process and operates with nominal 3 V supply with a power dissipation of less than 100 /spl mu/W at a 100 kHz frequency.