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Interface engineering for enhanced electron mobilities in W/HfO/sub 2/ gate stacks
By: Andreoni, W.; Curioni, A.; Gribelyuk, M.; Jammy, R.; Feely, F.M.; Lacey, D.; Shepard, J.; D'Emic, C.; Narayanan, V.; Gusev, E.; Zafar, S.; Carrier, E.; Jamison, P.; Callegari, A.; Pignedoli, C.;
2004 / IEEE / 0-7803-8684-1
This item was taken from the IEEE Conference ' Interface engineering for enhanced electron mobilities in W/HfO/sub 2/ gate stacks ' Electron mobilities of W/HfO/sub 2/ stacks were found to increase monotonically with annealing temperature with little (peak) or no degradation (1 MV/cm) when compared to poly-Si devices using conventional oxides. For stacks annealed at high temperature charge pumping curves indicate low interface states densities of /spl sim/5 /spl times/ 10/sup 10/ charges/cm/sup 2/. Mobility enhancement can also be attributed to a structural change in the HfO/sub 2/ gate stack rather than due to only interfacial layer re-growth.
Interfacial Layer Re-growth
High-k Gate Dielectrics
Interface States Densities
High Temperature Charge Pumping Curves
W/hfo/sub 2/ Gate Stacks
Insulated Gate Field Effect Transistors
Semiconductor Device Breakdown