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Aggressively scaled (0.143 /spl mu/m/sup 2/) 6T-SRAM cell for the 32 nm node and beyond

By: Fried, D.M.; Guarini, K.W.; Hergenrother, J.M.; Topol, A.W.; Chang, L.; Sekaric, L.; Sleight, J.W.; McNab, S.J.; Newbury, J.; Steen, S.E.; Gibson, G.; Zhang, Y.; Fuller, N.C.M.; Bucchignano, J.; Lavoie, C.; Cabral Jr, C.; Canaperi, D.; Dokumaci, O.; Frank, D.J.; Duch, E.A.; Babich, I.; Wong, K.; Ott, J.A.; Adams, C.D.; Dalton, T.J.; Nunes, R.; Medeiros, D.R.; Viswanathan, R.; Ketchen, M.; Ieong, M.; Haensch, W.;

2004 / IEEE / 0-7803-8684-1


This item was taken from the IEEE Conference ' Aggressively scaled (0.143 /spl mu/m/sup 2/) 6T-SRAM cell for the 32 nm node and beyond ' A 0.143 /spl mu/m/sup 2/ 6T-SRAM cell has been fabricated using a planar SOI technology with mixed electron-beam and optical lithography. This is the smallest functional 6T-SRAM cell ever reported - consistent with cell areas beyond the 32 nm technology node. Enabling process features include a 25 nm SOI layer, shallow trench isolation (STI), 45 nm physical gates with ultra-narrow 15 nm spacers, novel extremely thin cobalt disilicide, 50 nm tungsten plug contacts, and damascene copper interconnects. Device threshold voltages (V/sub T/) and cell beta ratio (/spl beta/) are optimized for cell stability at these aggressive ground rules. The 0.143 /spl mu/m/sup 2/ 6T-SRAM cell exhibits a static noise margin (SNM) of 148 mV at V/sup DD/=1.0 V.