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Systematic study of pFET V/sub t/ with Hf-based gate stacks with poly-Si and FUSI gates
By: Jamison, P.; Cabral, C., Jr.; Gusev, E.P.; Narayanan, V.; Cartier, E.; Jammy, R.; Guha, S.; Lacey, D.; Newbury, J.; D'Emic, C.; Carruthers, R.; Linder, B.; Chudzik, M.P.; Gribelyuk, M.; Callegari, A.; Zafar, S.; Cohen, S.A.; Copel, M.; Bojarczuk, N.; Frank, M.; Chan, K.K.; Steen, M.;
2004 / IEEE / 0-7803-8289-7
This item was taken from the IEEE Conference ' Systematic study of pFET V/sub t/ with Hf-based gate stacks with poly-Si and FUSI gates ' The flatband/threshold voltages (V/sub fb//V/sub t/) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO/sub 2/ at poly-Si deposition temperatures is identified as the root cause for the poor V/sub fb//V/sub t/ control. No improvement in V/sub t/ control is obtained by engineering physically closed Si/sub 3/N/sub 4/ barrier layers on HfO/sub 2/. It is furthermore shown for the first time that even when the gate is fully silicided (FUSI) large V/sub fb//V/sub t/ shifts are observed with HfO/sub 2/. Reduced pFET shifts are observed when Hf-silicates with low Hf content are used and further improvements are observed by using Al/sub 2/O/sub 3/ cap layers on silicates.
Rapid Thermal Processing
Si/sub 3/n/sub 4/
Hf-based Gate Stacks
Pfet V/sub T/
Al/sub 2/o/sub 3/
Cmos Integrated Circuits