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Leaky large area gate capacitance extraction for nanometer CMOS technology used for RF applications
By: Shimasue, M.; Aoki, H.;
2004 / IEEE / 0-7803-8423-7
This item was taken from the IEEE Conference ' Leaky large area gate capacitance extraction for nanometer CMOS technology used for RF applications ' In this research accurate capacitance measurement and extraction methods are demonstrated for very thin and large area gate oxide films. We first developed a gate capacitance model which includes any parasitic components and a gate leakage current model, and an interconnect de-embedding procedure which makes accurate measurements possible at the frequency ranges from 100MHz to 4GHz using relatively small gate capacitance TEG's. The target gate capacitance which has large gate area has been finally extracted by using the developed method, SPDC.
Integrated Circuit Modelling
Microwave Integrated Circuits
0.1 To 4 Ghz
Gate Capacitance Extraction
Nanometer Cmos Technology
Leakage Current Model
Interconnect De-embedding Procedure
Semiconductor Device Modeling
Integrated Circuit Interconnections
Uhf Integrated Circuits