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An efficient pre-layout on-chip inductance noise modeling tool for bus design

By: Lei Sun; Chiprout, E.; Husain, A.; Grannes, D.; Menon, S.; Bohnke, R.; Mazumder, M.; Changhong Dai; Eells, J.;

2003 / IEEE / 0-7803-8128-9


This item was taken from the IEEE Conference ' An efficient pre-layout on-chip inductance noise modeling tool for bus design ' On-chip inductance noise is becoming an increasingly important part of the total noise, particularly for global on-chip interconnects, because of faster transistor speeds and higher drive currents. An efficient pre-layout tool has been developed for accurate analysis of high frequency inductance effects on bus design. Since the return loop for inductance is not known a priori, a novel technique has been developed for fast determination of the inductance extraction window size to include all significant couplings and a sufficient number of power/ground return conductors. In addition, an algorithm has been developed for worst-case vector generation to estimate worst-case peak noise. The tool includes a methodology to determine the impact of power supply noise on bus crosstalk noise. It integrates RLC extraction, netlist generation, automatic worst-case vector generation, transient simulation, optimization, and post-processing of the simulated results to calculate noise, delay, and other signal integrity metrics. We demonstrate its application on optimal bus design by a microprocessor design group.