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Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication

By: Frank, D.J.; Singh, D.V.; Shi, L.; Newport, M.R.; Yu, R.; Ieong, M.; Topol, A.W.; Guarini, K.W.; Haensch, W.E.; Purushothaman, S.; Pogge, H.B.; Tempest, S.L.; O'Neil, P.A.; Boyd, D.C.; Nitta, S.V.; Cohen, G.M.;

2002 / IEEE / 0-7803-7462-2

Description

This item was taken from the IEEE Conference ' Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication ' We introduce a new scheme for building three-dimensional (3D) integrated circuits (ICs) based on the layer transfer of completed devices. We demonstrate for the first time that the processes required for stacking active device layers preserve the intrinsic electrical characteristics of state-of-the-art short-channel MOSFETs and ring oscillator circuits, which is critical to the success of high performance 3D ICs.