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An integrated tool for analog test generation and fault simulation
By: Ozev, S.; Orailoglu, A.;
2002 / IEEE / 0-7695-1561-4
This item was taken from the IEEE Conference ' An integrated tool for analog test generation and fault simulation ' High levels of design integration and increasing number of analog blocks within a system necessitate automated system-level analog test generation and fault simulation tools. We outline a methodology and toolset for specification-based automated test generation and fault simulation for analog circuits. Test generation is targeted at providing the highest coverage for each specified parameter. The flexibility of assigning analog test attributes is utilized for merging tests leading to test time reduction with no loss in test coverage. Further optimization in test time is obtained through fault simulations by selecting tests that provide adequate coverage in terms of several components and dropping the ones that do not provide additional coverage. The generated test set, fault and yield coverages in terms of each targeted parameter, and testability problems are reported by the tool.
Integrated Circuit Testing
Automated Analog Test Generation
System-level Analog Test Generation
Test Time Optimization
System Level Constraints
Test Set Compaction
Analogue Integrated Circuits
Test Time Reduction