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An architectural level energy reduction technique for deep-submicron cache memories
By: Asada, K.; Ishihara, T.;
2002 / IEEE / 0-7695-1441-3
This item was taken from the IEEE Conference ' An architectural level energy reduction technique for deep-submicron cache memories ' An architectural level technique for a high performance and low energy cache memory is proposed in this paper. The key idea of our approach is to divide a cache memory into several number of cache blocks and to activate a few parts of the cache blocks. The threshold voltage of each cache block is dynamically changed according to the utilization of each block. Frequently accessed cache blocks are woken up and others are put to sleep by controlling the threshold voltage. Since time overhead to change the threshold voltage can not be neglected, predicting a cache block which will be accessed in the next cycle is important. A history based prediction technique to predict cache blocks which should be woken up is also proposed. Experimental results demonstrated that the leakage energy dissipation in cache memories optimized by this approach can be less than 5% of energy dissipation in a cache memory which does not employ the approach.
Integrated Circuit Design
Leakage Energy Dissipation
Architectural Level Energy Reduction Technique
Architectural Level Technique
Cache Block Activation
Cache Block Utilization
Frequently Accessed Cache Blocks
Cache Block Access Prediction
History Based Prediction Technique
Very Large Scale Integration
Dynamically Changed Threshold Voltage