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3D integrated circuit using large grain polysilicon film

By: Chan, V.W.C.; Chan, P.C.H.; Mansun Chan;

2001 / IEEE / 0-7803-6520-8

Description

This item was taken from the IEEE Conference ' 3D integrated circuit using large grain polysilicon film ' 3-D CMOS IC technology built on two layers of large grain polysilicon is presented. These stacked layers are vertically interconnected allowing shorter interconnect to improve the logic speed. The large grain polysilicon-on-insulator (LPSOI) film is formed by the recrystallization of amorphous silicon through Metal Induced Lateral Crystallization (MILC). The crystallization region obtained can cover multiple transistors and the grain size is much larger than the transistor size. An oxide layer separates two layers of devices and forms an interlayer dielectric. The electrical performance of the LPSOI devices is presented. Inverters, ring-oscillators and shift registers further confirm that the recrystallized techniques forming the 3-D structures are feasible.