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Low S/D resistance FDSOI MOSFETs using polysilicon and CMP
By: Chan, P.C.H.; Chan, V.W.C.; Chunshan Yin;
2001 / IEEE / 0-7803-6714-6
This item was taken from the IEEE Conference ' Low S/D resistance FDSOI MOSFETs using polysilicon and CMP ' In this paper, we report fully depleted silicon-on-insulator (FDSOI) MOSFETs with polysilicon (poly) raised source and drain (S/D) by using chemical mechanical polish (CMP). This poly-raised FDSOI MOSFET, with channel thickness of 30 nm and deposited poly thickness of 80 nm, has shown a 95% reduction in source and drain series resistance and 90% reduction in contact resistance, compared with conventional FDSOI devices with the same channel thickness and without polysilicon at the S/D region. Silicide can be used to further reduce the active resistance.
Chemical Mechanical Polishing
Fully Depleted Silicon-on-insulator Mosfets
Fully Depleted Soi Mosfets
Polysilicon Raised Source/drain
Poly-raised Fdsoi Mosfet
Deposited Poly Thickness
Source/drain Series Resistance
Silicon On Insulator Technology
Semiconductor Device Measurement
Chemical Mechanical Polish