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High-speed low-power sense comparator for multilevel flash memories
2000 / IEEE / 0-7803-6542-9
This item was taken from the IEEE Conference ' High-speed low-power sense comparator for multilevel flash memories ' This paper presents a voltage comparator designed for use in high-performance sense circuits for multilevel flash memories. The comparator is made up by an input buffering stage followed by a regenerative gain stage. A fully differential scheme and offset compensation of both stages allows resolution and speed requirements to be met. Separate supply voltages are used for the two stages to guarantee the required large input common-mode range and, simultaneously, minimise power consumption from the high-voltage supply which is provided by a charge-pump based voltage multiplier. Simulation results show an overall comparison time within 20 ns (input signal 10 mV) with a current drain of 15 /spl mu/A from the high-voltage generator, which makes the proposed comparator well suited to multilevel sensing.
High-speed Integrated Circuits
Low-power Sense Comparator
Multilevel Flash Memories
Input Buffering Stage
Regenerative Gain Stage
Large Input Common-mode Range
Charge-pump Based Voltage Multiplier
Overall Comparison Time
Personal Digital Assistants
Fully Differential Scheme