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Construction of polyvalent error control codes for multilevel memories

By: Micheloni, R.; Ferrari, P.; Gregori, S.; Torelli, G.;

2000 / IEEE / 0-7803-6542-9

Description

This item was taken from the IEEE Conference ' Construction of polyvalent error control codes for multilevel memories ' The introduction of the multilevel storage approach and the advances in semiconductor memory technology towards higher-density chips create new reliability challenges for the memory designer. This paper presents a method to construct polyvalent error control codes for multilevel memories, which protect data stored in memory cells working at a variable number of bits per cell. The obtainable error control scheme allows a flexible use of multilevel memories assuring required data protection by exploiting the same encoding/decoding circuit and check cells. Implementation aspects of an encoding/decoding circuit are also discussed.