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Three dimensional CMOS integrated circuits on large grain polysilicon films

By: Chan, V.W.C.; Chan, M.; Chan, P.C.H.;

2000 / IEEE / 0-7803-6438-4

Description

This item was taken from the IEEE Conference ' Three dimensional CMOS integrated circuits on large grain polysilicon films ' In this paper, we report high performance three-dimensional (3-D) CMOS integrated circuits. The first layer of transistors is fabricated on Silicon-on-Insulator (SOI) and second layer is fabricated on large-grain polysilicon-on-insulator (LPSOI) film, with oxide as the interlayer dielectric. The LPSOI film is formed by the re-crystallization of amorphous silicon through metal-induced lateral crystallization (MILC) at an elevated temperature. Compared with the conventional 2-D CMOS SOI low-voltage circuit, 3D circuit shows significant reduction in circuit area, shorter propagation delay and lower dynamic power consumption.